AT32WB415
Series Reference Manual
2022.04.13
Page 137
Ver 2.00
12.2 Full-duplex/half-duplex selector
The full-duplex and half-duplex selector enables USART to perform data exchanges with peripherals in
full-duplex or half-duplex mode, which is achieved by setting the corresponding registers.
In two-wire unindirectional full-duplex mode (by default), TX pin is used for data output, while the RX pin
is used for data input. Since the transmitter and receiver are independent of each other, USART is
allowed to send/receive data at the same time so as to achieve full-duplex communication.
When the HALFSEL is set 1, the single-wire bidirectional half-duplex mode is selected for communication.
In this case, the LINEN, CLKEN, SCMEN and IRDAEN bits must be set 0. RX pin is inactive, while TX
and SW_RX are interconnected inside the USART. For the USART part, TX pins is used for data output,
and SW_RX for data input. For the peripheral part, bidirectional data transfer is executed through IO
mapped by TX pin.
12.3 Mode selector
12.3.1 Introduction
USART mode selector allows USART to work in different operation modes through software
configuration so as to enable data exchanges between USART and peripherals with different
communication protocols.
USART supports NRZ standard format (Mark/Space), by default. It also supports LIN (Local
Interconnection Network), IrDA SIR (Serial Infrared), Asynchronous Smartcard protocol in ISO7816-3
standard, RS-232 CTS/RTS (Clear To Send/Request To Send) hardware flow operation, silent mode and
synchronous mode, depending on USART mode selection configuration.
12.3.2 Configuration procedure
Selection of operation mode is done by following the configuration process listed below. In addition, such
configuration method, along with that of receiver and transmitter described in the subsequent sections,
are used to make USART initialization configuration.
1.
LIN mode: While LINEN bit is set 1, CLKEN, STOPBN[1: 0], SCMEN, SLHDEN, IRDAEN and DBN
bits are all set 0. 11-bit or 10-bit break frame detection depends on whether the BFBN bit is set 1 or
0. When the SBF bit is set 1, the 13-bit low-level LIN synchronous break frame is transmitted.
2.
Smartcard mode: SCMEN bit is set 1, LINEN, SLHDEN and IRDAEN bits are 0, CLKEN, DBN and
PEN bits are set 1, and STOPBN[1: 0]=11. The polarity, phase and pulse number of the clock can
be configured by setting the CLKPOL, CLKPHA and LBCP bits (Refer to Synchronous mode for
details). The SCGT[7: 0] bit is used to select protection time. The SCNACKEN bit is used to select
whether to send NACK when parity error occurs.
3.
Infrared mode: IRDAEN is set 1, and the CLKEN, STOPBN[1: 0], SCMEN and SLHDEN bits are all
0. Set the IRDALP bit enables infrared low-power mode, and configures the desired low-power
frequency in conjunction with the ISDIV[7:0].
4.
Hardware flow control mode: Set the RTSEN and CTSEN bit will enable RTS and CTS flow control,
respectively.
5.
Silent mode:When the RM bit is set, it enters silent mode. When the WUM bit is set 1 or 0, it wakes
up from silent mode through ID match and idle bus, respectively. The ID[3: 0] is configurable. When
ID match is selected, if the MSB of data bit is set, it indicates that the current data is ID, the four LSB
represents ID value.
6.
Synchronous mode: Set the CLKEN bit enables synchronous mode and clock pin output. Select CK
pin high or low in idle state by setting the CLKPOL bit (1 or 0). Whether to sample data on the second
or first edge of the clock depends on the CLKPHA bit (1 or 0). The LBCP bit (1 or 0) is used to select
whether to output clock on the last data bit. And the ISDIV[4: 0] is used to select the required clock
output frequency.
