AT32WB415
Series Reference Manual
2022.04.13
Page 326
Ver 2.00
empty, the controller generates an INCOMPISOIN interrupt in the OTGFS_GINTSTS register.
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Application programming sequence (frame transfers)
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1. Program the OTGFS_DIEPTSIZx register
2. Program the OTGFS_DIEPCTLx register based on endpoint characteristics, and set the CNAK and
endpoint enable bits
3. Write the data to be transmitted into the transmit FIFO.
4. The assertion of the INTKNTXFEMP interrupt indictes that the application has not yet written all data
to be transferred into the transmit FIFO.
5. If the interrupt endpint is already enabled while this interrupt is detected, ignore the interrupt. If it is
not enabled, enable the endpoint to transmit data on the next IN token. If it is enabled while the
interrupt is detected, refere to “Incomplete synchronous IN data transfers”.
6. When the interrupt IN endpoint is set as a periodic endpoint, the controller internally can process the
timeout on the interrupt IN endpoint, without the need of the application intervention. Therefore, the
application can never detect the TIMEOUT interrupt (in the OTGFS_DIEPINTx register) on the
periodic interrup IN endpoints.
7. The assertion of the XFERC interrupt in the OTGFS_DIEPINTx register but without the
INTKNTXFEMP interrupt indicates the successful completion of a synchronous IN transfer. When
reading the OTGFS_DIEPTSIZx register, only transfer size =0 and packet count =0 indicate that all
data are transmitted on the USB line.
8. The assertion of the XFERC interrupt in the OTGFS_DIEPINTx register, with or without the
INTKNTXFEMP interrupt, indicates the successful completion of an interrupt IN transfer. When
reading the OTGFS_DIEPTSIZx register, only transfer size =0 and packet count =0 indicate that all
data are transmitted on the USB line.
9. The assertion of the INCOMPISOIN interrupt but without the above-mentioned interrupts indicates
that the controller did not receive at least one periodic IN token in the current frame. Refer to
“Incomplete synchronous IN data transfers” for more information on synchronous IN endpoints.
20.6 OTGFS control and status registers
The application controls the OTGFS controller by reading from and writing to the control and status
registers (CSRx) through the AHB slave interface. These registers are accessible by 32 bits, and the
addresses are 32-bit aligned.
Only the controller global, power and clock control, data FIFO access and host port control and status
registers are active in both host and device modes. When the OTGFS controller operates in either host
or device mode, the application must not access the register group from the other mode. If an illegal
access occurs, a mode mismatch interrupt is generated and the MODMIS bit (in the OTGFS_GINTSTS
register) is affected.
When the controller switches from one mode to the other, the registers in the new mode must be re-
initialized as they are after a power-on reset. These peripheral registers must be accessed by words
(32-bit)
20.6.1 CSR register map
The host and device mode registers occupy different addresses. All registers are located in the AHB
clock domain
Figure 20-13 CSR memory map
