ARTERY AT32WB415 Series, Reference Manual

Page: 366 / 374

AT32WB415 Series Reference Manual
2022.04.13 Page 366 Ver 2.00
21.3 Interrupt management
Comparator 1 generates an external interrupt or event via EXTI line 19 to wakeup device from low-power
mode;
Comparator 2 generates an external interrupt or event via EXTI line 20 to wakeup device from low-power
mode.
For more detailed information, please refer to the section of interrupts and events.
21.4 Design tips
The following information can be used for design reference:
 Input/Output configuration
As a comparator input, the I/Os must be configuread as an analog mode. The comparator output
can be remapped onto external I/Os through the CMP_MUX[1: 0] bit in the IOMUX_REMAP2
register.
Comparator output configuration:
Multiplexed
CMP_MUX
[1: 0]=00 CMP_MUX
[1: 0]=01 CMP_MUX
[1: 0]=10
CMP1_OUT PA0 PA6 PA11
CMP2_OUT PA2 PA7 PA12
 Lock
The CMP_CTRLSTS1 register can be write-protected. By setting CMPxWP=1, the corresponding
bits in the CMP_CTRLSTS1 and CMP_CTRLSTS2 registers can be read-only after the completion
of programming, and even the CMPxWP can be unlocked only after a system reset. This feature
can be used for the applications with specific security requirements.
 Low-power mode
The comparator is clocked by the PCLK, and uses system reset as its reset signal. The comparator
still works in Deepsleep mode, which can be used as an EXINT interrupt source to wakeup device
from low-power mode.
21.5 Functional overview
21.5.1 Analog comparator
Positive/Negative input selection
Select an I/O as a positive intput source through the CMPxNINVSEL[1: 0] bit in the CMP_CTRLSTS1
register; Select an internal reference voltage, three voltage divider values or an I/O as a negative input
source through the CMPxINVSEL[2: 0] bit.
Hysteresis
The hysteresis feature can be selected through the CMPxHYST[1: 0] bit in the CMP_CTRLSTS1 register.
This is used to avoid fake signal caused by noise. Hysteresis can be disabled (exit low-power mode) if
not needed.
Operating mode
The controller can operate in fast speed/maximum power consumptioin, low speed/lowest power
consumption in order to achieve the best trade-off between performance and power consumption, which
is selected through the CMPxSSEL bit in the CMP_CTRLSTS1 register.