AT32WB415
Series Reference Manual
2022.04.13
Page 327
Ver 2.00
The overall situation of the core CSRs(1024 byte)
Host mode CSRs (1024 byte)
Device mode CSRs (1024 byte)
Power and clock control CSRs (512 byte)
Equipment EP 0/host channel 0 FIFO (4096 byte)
Equipment EP 1/host channel 1 FIFO (4096 byte)
Equipment Epx (1)/host channel x (1) FIFO (4096 byte)
Equipment EP(x-1) (1)/host channel (x-1) (1) FIFO (4096
byte)
Retain
Data directly accessed during debugging FIFO RAM
(131072 byte)
DFIFO
Read/write in
this area
push/pop
DFIFO
Read/write in
this area
during
debugging
0000h
0400h
0800h
0E00h
1000h
2000h
3000h
0F000h
10000h
11000h
20000h
3FFFFh
x = 4 in device mode, x =8 in host mode.
The OTGFS control and status registers contain OTGFS global register, host mode register, device
mode register, data FIFO register, power and clock control register.
1. OTGFS global registers: They are active in both host and device modes. The register acronym is
G.
2. Host-mode registers: They must be programmed every time the controller changes to host mode,
The register acronym is H.
3. Device-mode registers: They must be programmed every time the controller changes to
device mode, The register acronym is D.
4. Data FIFO access registers: These registers are valid in both in host and device modes, and are
used to read or write the FIFO for a specific endpoint or channel in a given direction. If a host
channel is of type IN, the FIFO can only be read. Similarily, if a host channel is of type OUT, the
FIFO can only be written.
5. Power and clock control register: There is only one regiser for power and clock control. It is valid in
both host and device modes.
