Pulse-Width Modulation Subsystem (PWMSS)
15.1.2.2 PWMSS Clock and Reset Management
The PWMSS controllers have separate bus interface and functional clocks.
Table 15-3. PWMSS Clock Signals
Clock Signal
Max Freq
Reference / Source
Comments
PWMSS_ocp_clk
100 MHz
CORE_CLKOUTM4 / 2
pd_per_l4ls_gclk
Interface / Functional clock
from PRCM
15.1.2.3 PWMSS Pin list
The external signals for the PWMSS module are shown in the following table.
Table 15-4. PWMSS Pin List
Pin
Type*
Description
EPWMxA
O
PWM output A
EPWMxB
O
PWM output B
EPWM_SYNCIN
I
PWM Sync input
EPWM_SYNCOUT
O
PWM Sync output
EPWM_TRIPZONE[5:0]
I
PWM Tripzone inputs
ECAP_CAPIN_APWMOUT
I/O
eCAP Capture input / PWM output
EQEP_A
I/O
eQEP Quadrature input/output
EQEP_B
I/O
eQEP Quadrature input/output
EQEP_INDEX
I/O
eQEP Index input/output
EQEP_STROBE
I/O
eQEP Strobe input/output
15.1.3 PWMSS Registers
lists the memory-mapped registers for the PWMSS. All register offset addresses not listed in
should be considered as reserved locations and the register contents should not be modified.
Table 15-5. PWMSS REGISTERS
Offset
Acronym
Register Name
Section
0h
IDVER
IP Revision Register
4h
SYSCONFIG
System Configuration Register
8h
CLKCONFIG
Clock Configuration Register
Ch
CLKSTATUS
Clock Status Register
1489
SPRUH73H – October 2011 – Revised April 2013
Pulse-Width Modulation Subsystem (PWMSS)
Copyright © 2011–2013, Texas Instruments Incorporated