Ethernet Subsystem Registers
14.5.8.2 CONTROL Register (offset = 4h) [reset = 0h]
CONTROL is shown in
and described in
.
SWITCH CONTROL REGISTER
Figure 14-185. CONTROL Register
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
Reserved
7
6
5
4
3
2
1
0
Reserved
DLR_EN
RX_VLAN_ENCAP
VLAN_AWARE
FIFO_LOOPBACK
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-202. CONTROL Register Field Descriptions
Bit
Field
Type
Reset
Description
3
DLR_EN
R/W-0
0
DLR enable
0 - DLR is disabled.
DLR packets will not be moved to queue priority 3 and will not be
separated out onto dlr_cpdma_ch.
1 - DLR is disabled.
DLR packets be moved to destination port transmit queue priority 3
and will be separated out onto dlr_cpdma_ch when packet is to
egress on port 0.
2
RX_VLAN_ENCAP
R/W-0
0
Port 0 VLAN Encapsulation (egress):
0 - Port 2 receive packets (from 3G) are not VLAN encapsulated.
1 - Port 2 receive packets (from 3G) are VLAN encapsulated.
1
VLAN_AWARE
R/W-0
0
VLAN Aware Mode:
0 - 3G is in the VLAN unaware mode.
1 - 3G is in the VLAN aware mode.
0
FIFO_LOOPBACK
R/W-0
0
FIFO Loopback Mode
0 - Loopback is disabled
1 - FIFO Loopback mode enabled.
Each packet received is turned around and sent out on the same
port's transmit path.
Port 2 receive is fixed on channel zero.
The RXSOFOVERRUN statistic will increment for every packet sent
in FIFO loopback mode.
1426
Ethernet Subsystem
SPRUH73H – October 2011 – Revised April 2013
Copyright © 2011–2013, Texas Instruments Incorporated