Programming Model
13.4.1.2 CPU Initiated Data Bus Transactions
13.4.1.2.1 Initiating Data Bus Transactions
Writing to cfg_cs0_data will initiate a write transfer to the CS0 panel. Reading from cfg_cs0_data will
initiate a read transfer from the CS0 panel.
Writing to cfg_cs1_data will initiate a write transfer to the CS1 panel. Reading from cfg_cs1_data will
initiate a read transfer from the CS0 panel.
NOTE:
Writes to CS1 translate to valid bus transactions only if cfg_lidd_mode_sel[2:0] is configured
for an asynchronous mode.
13.4.1.3 DMA Initiated Data Bus Transactions for LIDD
13.4.1.3.1 DMA Overview for MPU Bus Output
Writing a long sequence of data to the Character Display Panel will ensure that the CPU will be occupied
for a long time. However, the DMA module supports a mode in which this sequence of data elements can
first be written in DRAM by the CPU.
The DMA can read this sequence of commands or data from the DRAM and send it to the LCD Interface
Display Driver (LIDD) module such that each data element becomes a write bus transaction to the
external Character Panel/MPU Bus. The data bus write transaction can target either CS0 or CS1 and use
the appropriate bus timing parameters.
Functionally, in this DMA LIDD mode, the DMA module sends the sequence of data to the LIDD module
by acting as another CPU.
The DMA can only perform write bus transactions. It cannot read from the external character panel a
series of data elements and store them in the DRAM.
When the LIDD module is controlled by the DMA module by setting cfg_lidd_dma_en = ‘1’, CPU reads or
writes to cfg_adr_index and cfg_data are not allowed.
The fb0_base and fb0_ceil registers define the address boundary of data elements to be sent out the
character display by the DMA engine. Setting cfg_lidd_dma_en from ‘0’ to ‘1’ will initiate the DMA as if a
virtual CPU is reading data from the DDR and writing the values to Reg6 or Reg9. cfg_dma_cs0_cs1
determines whether the virtual CPU writes to Reg6 (CS0) or Reg7 (CS1).
NOTE:
Writes to CS1 translate to valid bus transactions only if cfg_lidd_mode_sel[2:0] is configured
for an asynchronous mode.
The DMA module requires the start and end DDR addresses to be on word-aligned byte addresses. The
MPU/LIDD bus is a halfword (16 bit) output, so both the upper and lower halfwords of the DDR memory
will be sent out. Thus, the number of data elements sent to the LIDD by the DMA must always result in an
even number of bus MPU bus transactions. In other words, a transfer of three 32-bit words from DDR will
result in six 16-bit bus transactions.
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SPRUH73H – October 2011 – Revised April 2013
LCD Controller
Copyright © 2011–2013, Texas Instruments Incorporated
