UART Registers
19.5.1.6 Interrupt Identification Register (IIR) - UART Mode
The UART interrupt identification register (IIR) is a read-only register that provides the source of the
interrupt. The UART interrupt identification register (IIR) is shown in
and described in
.
NOTE:
An interrupt source can be flagged only if enabled in the IER register.
Figure 19-39. UART Interrupt Identification Register (IIR)
15
8
Reserved
R-0
7
6
5
1
0
FCR_MIRROR
IT_TYPE
IT_PENDING
R-0
R-0
R-1
LEGEND: R = Read only; -n = value after reset
Table 19-35. UART Interrupt Identification Register (IIR) Field Descriptions
Bit
Field
Value
Description
15-8
Reserved
0
Reserved.
7-6
FCR_MIRROR
0-3h
Mirror the contents of FCR[0] on both bits.
5-1
IT_TYPE
0-1Fh
Seven possible interrupts in UART mode; other combinations never occur:
0
Modem interrupt. Priority = 4.
1h
THR interrupt. Priority = 3.
2h
RHR interrupt. Priority = 2.
3h
Receiver line status error. Priority = 1.
4h-5h
Reserved
6h
Rx timeout. Priority = 2.
7h
Reserved
8h
Xoff/special character. Priority = 5.
9h-Fh
Reserved
10h
CTS, RTS, DSR change state from active (low) to inactive (high). Priority = 6.
11h-
Reserved
1Fh
0
IT_PENDING
Interrupt pending.
0
An interrupt is pending.
1
No interrupt is pending.
3511
SPRUH73H – October 2011 – Revised April 2013
Universal Asynchronous Receiver/Transmitter (UART)
Copyright © 2011–2013, Texas Instruments Incorporated