Memory Region 0
Base Address
Memory Region 1
Base Address
Memory Region 2
Base Address
Memory Region N
Base Address
Region N
64 x 32
Bytes
Region 2
64 x 32
Bytes
Region 1
32 x 64
Bytes
Region 0
128 x 32
Bytes
0
64
Entries
Index w
Index x
Index y
128
Entries
64 Entries
32
Entries
Index z
65535
Linking RAM
Region 1
Linking RAM
Region 0
Functional Description
To accomplish the linking of submitted descriptors, the queue manager will first resolve the 32-bit
descriptor pointer into a 16-bit index which is used for linking and queue pointer purposes. Once the
physical index information is determined, the queue manager will link that descriptor onto the descriptor
chain that is maintained for that logical queue by writing the linking information out to a linking RAM which
is external to the queue manager. The queue manager will also update the queue tail pointer
appropriately. Since logical queues within the queue manager are maintained using linked lists, queues
cannot become full and no check for fullness is required before queuing a packet descriptor.
The actual physical size of the Linking RAM region(s) to be allocated depends on the total number of
descriptors defined within all memory regions. A minimum of four bytes of memory needs to be allocated
for each Descriptor defined within all 16 memory regions.
The queue manager has the capability of managing up to 16 memory regions. These memory regions are
used to store descriptors of variable sizes. The total number of descriptors that can be managed by the
queue manager should not exceed 64K. Each memory region has descriptors of one configurable size,
that is, descriptors with different sizes cannot be housed within a single memory region. These 64K
descriptors are referenced internally in the queue manager by a 16-bit quantity index.
The information about the Linking RAM regions and the size that are allocated is communicated to the
CPPI DMA via three registers dedicated for this purpose. Two of the three registers are used to store the
32-bit aligned start addresses of the Linking RAM regions. The remaining one register is used to store the
size of the first Linking RAM. The linking RAM size value stored here is the number of descriptors that is
to be managed by the queue manager within that region not the physical size of the buffer, which is four
times the number of descriptors.
Note that application is not required to use both linking RAM regions, if the size of the Linking RAM for the
first region is large enough to accommodate all descriptors defined. No linking RAM size register for
linking RAM region 2 exists. The size of the second linking RAM, when used, is indirectly computed from
the total number of descriptors defined less the number of descriptors managed by the first linking RAM
displays the relationship between several memory regions and linking RAM.
Figure 16-16. Relationship Between Memory Regions and Linking RAM
16.3.9.5 Zero Length Packets
A special case is the handling of null packets with the CPPI 4.1 compliant DMA controller. Upon receiving
a zero length USB packet, the XFER DMA will send a data block to the DMA controller with byte count of
zero and the zero byte packet bit of INFO Word 2 set. The DMA controller will then perform normal End of
Packet termination of the packet, without transferring data.
1746
Universal Serial Bus (USB)
SPRUH73H – October 2011 – Revised April 2013
Copyright © 2011–2013, Texas Instruments Incorporated