Pulse-Width Modulation Subsystem (PWMSS)
15.1.3.3 CLKCONFIG Register (offset = 8h) [reset = 111h]
CLKCONFIG is shown in
and described in
The clock configuration register is used in the PWMSS submodule for clkstop req and clk_en control.
Figure 15-4. CLKCONFIG Register
31
30
29
28
27
26
25
24
Reserved
R-0h
23
22
21
20
19
18
17
16
Reserved
R-0h
15
14
13
12
11
10
9
8
Reserved
ePWMCLKSTOP_RE
ePWMCLK_EN
Q
R-0h
R/W-0h
R/W-1h
7
6
5
4
3
2
1
0
Reserved
eQEPCLKSTOP_REQ
eQEPCLK_EN
Reserved
eCAPCLKSTOP_REQ
eCAPCLK_EN
R-0h
R/W-0h
R/W-1h
R-0h
R/W-0h
R/W-1h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 15-8. CLKCONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
31-10
Reserved
R
0h
9
ePWMCLKSTOP_REQ
R/W
0h
This bit controls the clkstop_req input to the ePWM module.
8
ePWMCLK_EN
R/W
1h
This bit controls the clk_en input to the ePWM module.
7-6
Reserved
R
0h
5
eQEPCLKSTOP_REQ
R/W
0h
This bit controls the clkstop_req input to the eQEP module
4
eQEPCLK_EN
R/W
1h
This bit controls the clk_en input to the eQEP module.
3-2
Reserved
R
0h
1
eCAPCLKSTOP_REQ
R/W
0h
This bit controls the clkstop_req input to the eCAP module.
0
eCAPCLK_EN
R/W
1h
This bit controls the clk_en input to the eCAP module.
1492
Pulse-Width Modulation Subsystem (PWMSS)
SPRUH73H – October 2011 – Revised April 2013
Copyright © 2011–2013, Texas Instruments Incorporated