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Date Code 990215 Inputs, Outputs, Timers, and Other Control Logic 7-17
SEL-351P Manual Técnico
Figure SECTION 7: .15: Time Line for Reset of Latch Bit LT2 After Active Setting
Group Change
In Figure SECTION 7: .15, latch bit LT2 is reset (deasserted to logical 0) when reset setting
RST2 asserts to logical 1 for the short time right after setting Group 4 is activated. This logic
can be repeated for other latch bits.
Note: Make Latch Control Switch Settings with Care
The latch bit states are stored in nonvolatile memory so they can be retained during power loss,
settings change, or active setting group change. The nonvolatile memory is rated for a finite
number of “writes” for all cumulative latch bit state changes. Exceeding this limit can result in
an EEPROM self-test failure. This limit translates to an average of 150 cumulative latch bit state
changes per day for a 25-year relay service life.
This requires that SEL
OGIC
Control Equation settings SETn and RSTn for any given latch bit
LTn (n = 1 through 8; see Figure SECTION 7: .11) be set with care. Settings SETn and RSTn
cannot result in continuous cyclical operation of latch bit LTn. Use timers to qualify conditions
set in settings SETn and RSTn. If any optoisolated inputs IN101 through IN106 are used in
settings SETn and RSTn, the inputs have their own debounce timer that can help in providing the
necessary time qualification (see Figure SECTION 7: .1).
In the preceding reclosing relay enable/disable example application (Figure SECTION 7: .13 and
Figure SECTION 7: .14), the SCADA contact cannot be asserting/deasserting continuously, thus
causing latch bit LT1 to change state continuously. Note that the rising edge operators in the
SET1 and RST1 settings keep latch bit LT1 from cyclically operating for any single assertion of
the SCADA contact.