Schweitzer Engineering SEL-351P, Быстрый старт

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5-4 Trip and Target Logic Date Code 990215
SEL-351P Manual Técnico
Unlatch Trip
Once Relay Word bit TRIP is asserted to logical 1, it remains asserted at logical 1 until all the
following conditions come true:
•
Minimum Trip Duration Timer stops timing (logic output of the TDURD timer goes to
logical 0)
•
Output of OR-1 gate deasserts to logical 0
•
One of the following occurs:
−
SEL
OGIC
Control Equation setting ULTR asserts to logical 1,
−
The front-panel TARGET RESET button is pressed,
−
Or the TAR R (Target Reset) command is executed via the serial port.
The front-panel TARGET RESET button or the TAR R (Target Reset) serial port command is
primarily used during testing. Use these to force the TRIP Relay Word bit to logical 0 if test
conditions are such that setting ULTR does not assert to logical 1 to automatically deassert the
TRIP Relay Word bit instead.
Other Applications for the Target Reset Function
Refer to the bottom of Figure 5.1. Note that the combination of the TARGET RESET
Pushbutton and the TAR R (Target Reset) serial port command is also available as Relay Word
bit TRGTR. See Figure 5.17 and accompanying text for applications for Relay Word bit
TRGTR.
Factory Settings Example (using setting TR)
If the “communications-assisted” and “switch-onto-fault” trip logic at the top of Figure
SECTION 5: .1 can effectively be ignored, the figure becomes a lot smaller. Then SEL
OGIC
Control Equation trip setting TR is the only input into OR-1 gate and follows into the “seal-in
and unlatch” logic for Relay Word bit TRIP.
The factory settings for the trip logic SEL
OGIC
Control Equation settings are:
TR = 51P1T + 51P2T + 51G1T + 51G2T + 51N1T + 51N2T
+ 67P2T + 67G2T + 67N2T + 67N3T + 81D1T + PB9 + OC
(trip conditions)
ULTR = 1 (always equal to logical 1) (unlatch trip conditions)
The factory setting for the Minimum Trip Duration Timer setting is:
TDURD = 4.00 cycles
With setting TDURD = 4.00 cycles, once the TRIP Relay Word bit asserts via SEL
OGIC
Control
Equation setting TR, it remains asserted at logical 1 for a minimum of 4 cycles.
Note: There is no need to set TDURD greater than 4 cycles. The final trip/close logic in
Figure 7.29 takes care of all timing issues concerning the dedicated trip output contact.
The TRIP Relay Word bit output of the trip logic in Figure SECTION 5: .1 (that follows
the TDURD timer) propagates to the final trip/close logic in Figure 7.29.