The parameters for the EnDat interface are described in Section "EnDat
(cyclical) X7" on page 62, as are the differences in using the EnDat interface with the
“cyclical” method and “one-time reading” method.
NOTE
l
Special TTL encoders with commutation tracks can be run on
encoder channel Ch3 (X8) by setting
P 507[0] - ENC_CH3_Sel
to
TTL_COM(5).
6.7.7 SSI (cyclical) X8
Ch3: SSI(2) - Cyclical SSI
The software versions required to run the SSI encoder interface are the standard
software versions for the ServoOne and ServoOne junior.
NOTE
l
Please note the limitations that apply when running EnDat and
SSI encoders (see Section "Limiting for EnDat and SSI" on page
52).
SSI (Synchronous Serial Interface) is a digital encoder interface that is supported by
a large number of manufacturers. It is not standardized, meaning that manufacturers
are free to support the interface as they like. The pseudo-standard described below
has however been established for motor feedback interfaces. KEBA supports this
version first and foremost.
The following table lists the parameters for cyclical SSI operation on encoder
channel Ch3. It also points out possible differences between the use of the SSI
interface with the “cyclical” method and “one-time reading” method when using
SinCos encoders with an SSI absolute value interface.
ID No.: 0842.26B.5-01 Date: 09.2020
ServoOne - Device Help
89
6 Encoder
SSI encoder basics and requirements
The SSI interface on the ServoOne has been designed as an actual motor feedback
interface. Accordingly, the connected SSI encoder must meet the following criteria:
l
Clock and data inactive level = HIGH
l
The current position must be internally stored at the first falling clock edge
l
No lengthened calculation time (in first cycle)
l
With the first rising clock edge, the encoder must shift the data to the first
position bit to be transmitted (MSB)
l
1 Mbps rate
l
Data coding = Binary or Gray
l
Reading data after the data bits end is permissible
l
125 µs cycle (i.e. internal position refresh rate
≪
125 µs)
l
Monoflop time ≥ 6 µs
l
Data lines driven with logic 0 during monoflop time
l
No parity bit
l
No error bits or other status bits
l
≤14 MultiTurn bits
SSI wire break monitoring (bit monitoring during monoflop time)
If monitoring is enabled, the controller, as the SSI clock master, will read data for one
more clock cycle after the data bits (reading data after the data bits end is
permissible). The bit that the master reads in addition to the data bits this way comes
from the SSI encoder’s monoflop time. At the time corresponding to this bit, the SSI
encoder must drive the data lines with a logic 0. If the data lines on connector X8 are
open, a logic 1 will be read here. The bit monitoring at this point makes it possible to
determine whether the SSI data lines are being actively driven with a logic 0 at this
point (no “wire break”) or are not (“wire break”). SSI wire break monitoring can be
disabled by setting P 576[0] - ENC_CH3_Mode to 0001h.