Hioki BT5525, Инструкция по эксплуатации, Страница: 120 / 215

120
Communications Method
Status Byte Register (STB)
The Status Byte Register (STB) is an 8-bit register in which information for the event register and
output queue is set.
The Status Byte Register (STB) is not cleared even if the
*STB?
query is executed. It is cleared
when the
*CLS
command is executed, however, the ERR bit is not cleared when there is an
instrument error.
Bit 7 – Unused
Bit 6
SRQ Unused
MSS
This represents the logical sum of the other bits of the Status Byte Register
(STB).
Bit 5 ESB
Standard event summary (logical sum) bit
This is the logical sum of the Standard Event Status Register.
It is cleared with the
*ESR?
command.
Bit 4 MAV
Message available
It is set to “1” when a message is present in the output queue.
Bit 3 – Unused
Bit 2 ERR
Error bit
It is set to “1” when there is error information.
It is cleared when error information is output with the
:SYSTem:ERRor?
command.
However, the bit is not cleared in the event of a hardware error.
Bit 1 – Unused
Bit 0 – Unused
Service Request Enable Register (SRER)
When each bit of the Service Request Enable Register (SRER) is set to “1”, the MSS bit is set to “1”
if any corresponding bit of the Status Byte Register (STB) changes from “0” to “1” and the MSS bit
is set to “0” when all the bits become “0”.
Any unused bits and bit 6 of the Status Byte Register (STB) are fixed as 0.
Standard Event Register information
Output queue data information
Error information
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
–
SRQ
ESB MAV – ERR – –
Status Byte Register
(STB)
MSS
AND AND AND
OR
– 0 ESB MAV – ERR – –
Service Request Enable
Register (SRER)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
HIOKI BT5525A961-00