Constraints and Notes
Freq
uency
System Clock Name
main_nand_sdmmc_clk
Input clock to flash controller
clocks block
FPGA manager configuration
clock
osc1_clk
to 125_MHz divided
from main PLL C5
cfg_clk
Auxiliary user clock to the FPGA
fabric
osc1_clk
to 100_MHz divided
from main PLL C5
h2f_user0_clock
Changing Values That Affect Main Clock Group PLL Lock
To change any value that affects VCO lock of the main clock group PLL, including the hardware-managed
clocks, software must put the main PLL in bypass mode, which causes all the main PLL output clocks to be
driven by the
osc1_clk
clock. Software must detect PLL lock by reading the lock status register prior to
taking the main PLL out of bypass mode.
Once a PLL is locked, changes to any PLL VCO frequency that are 20 percent or less do not cause the PLL
to lose lock. Iteratively changing the VCO frequency in increments of 20 percent or less allow a slow ramp
of the VCO base frequency without loss of lock.For example, to change a VCO frequency by 40% without
losing lock, change the frequency by 20%, then change it again by 16.7%.
Peripheral Clock Group
The peripheral clock group consists of a PLL, dividers, and clock gating. The clocks in the peripheral clock
group are derived from the peripheral PLL. The peripheral PLL can be programmed to be sourced from the
EOSC1
pin, the
EOSC2
pin, or the
f2h_periph_ref_clk
clock provided by the FPGA fabric.
The counter outputs from the main PLL can have their frequency further divided by external dividers.
Transitions to a different divide value occur on the fastest output clock, one clock cycle prior to the slowest
clock’s rising edge. For example, cycle 15 of the divide-by-16 divider for the main C2 output and cycle 3 of
the divide-by-4 divider for the C1 output.
Altera Corporation
Clock Manager
2-9
Changing Values That Affect Main Clock Group PLL Lock
cv_54002
2013.12.30
