Altera Cyclone V, Руководство по эксплуатации устройства

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Table 2-5: Peripheral Clock Group Clocks
Constraints and Notes Divided From Frequency System Clock Name
Clock for USB Peripheral PLL C4 Up to 200 MHz
usb_mp_clk
Clock for L4 SPI master
bus and scan manager Peripheral PLL C4 Up to 240 MHz for the SPI
masters and up to 200 MHz
for the scan manager
spi_m_clk
EMAC0 clock. The
250 MHz clock is
divided internally by the
EMAC into the typical
125/25/2.5 MHz speeds
for 1000/100/10 Mbps
operation. Peripheral PLL C0 Up to 250 MHz
emac0_clk
EMAC1 clock
. The 250 MHz clock is
divided internally by the
EMAC into the typical
125/25/2.5 MHz speeds
for 1000/100/10 Mbps
operation.
Peripheral PLL C1 Up to 250 MHz
emac1_clk
Clock for L4 master
peripheral bus Main PLL C1 or peripheral
PLL C4 Up to 100 MHz
l4_mp_clk
Clock for L4 slave
peripheral bus Main PLL C1 or peripheral
PLL C4 Up to 100 MHz
l4_sp_clk
Controller area network
(CAN) controller 0
clock Peripheral PLL C4 Up to 100 MHz
can0_clk
CAN controller 1 clock Peripheral PLL C4 Up to 100 MHz
can1_clk
Used to debounce
GPIO0, GPIO1, and
GPIO2 Peripheral PLL C4 Up to 1 MHz
gpio_db_clk
Auxiliary user clock to
the FPGA fabric Peripheral PLL C5 Peripheral PLL C5
h2f_user1_
clock
SDRAM Clock Group
The SDRAM clock group consists of a PLL and clock gating. The clocks in the SDRAM clock group are
derived from the SDRAM PLL. The SDRAM PLL can be programmed to be sourced from the
EOSC1
pin,
the
EOSC2
pin, or the
f2h_sdram_ref_clk
clock provided by the FPGA fabric.
Clock Manager
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2013.12.30