Receiver Status
The PCIe specification requires that the PHY encode the receiver status on a 3-bit status signal
(
pipe_rxstatus[2:0]
).
This status signal is used by the PHY-MAC layer for its operation. The PIPE interface block receives the
status signals from the transceiver channel PCS and PMA blocks, and encodes the status on the
pipe_rxstatus[2:0]
signal to the FPGA fabric. The encoding of the status signals on the
pipe_rxstatus[2:0]
signal is compliant with the PCIe specification.
Receiver Detection
The PIPE interface block in Cyclone V transceivers provides an input signal
(
pipe_txdetectrx_loopback
) for the receiver detect operation that is required by the PCIe protocol
during the detect substate of the LTSSM.
When the
pipe_txdetectrx_loopback
signal is asserted in the P1 power state, the PCIe interface
block sends a command signal to the transmitter buffer in that channel to initiate a receiver detect sequence.
In the P1 power state, the transmitter buffer must always be in the electrical idle state.
After receiving this command signal, the receiver detect circuitry creates a step voltage at the output of the
transmitter buffer. If an active receiver that complies with the PCIe input impedance requirements is present
at the far end, the time constant of the step voltage on the trace is higher than if the receiver is not present.
The receiver detect circuitry monitors the time constant of the step signal that is seen on the trace to determine
if a receiver was detected. The receiver detect circuitry monitor requires a 125-MHz clock for operation that
you must drive on the
fixedclk
port.
For the receiver detect circuitry to function reliably, the AC-coupling capacitor on the serial link and
the receiver termination values used in your system must be compliant with the PCIe Base Specification
2.1.
Note:
The PCI Express PHY (PIPE) IP core provides a 1-bit PHY status (
pipe_phystatus
) and a 3-bit receiver
status signal (
pipe_rxstatus[2:0]
) to indicate whether a receiver was detected or not, in accordance
to the PIPE specifications.
Clock Rate Compensation Up to ±300 ppm
In compliance with the PCIe protocol, the receiver channels are equipped with a rate match FIFO to
compensate for the small clock frequency differences of up to ± 300 ppm between the upstream transmitter
and local receiver clocks.
Related Information
Transceiver Architecture in Cyclone V Devices
PCIe Reverse Parallel Loopback
The PCIe reverse parallel loopback is only available in the PCIe functional configuration for the Gen1 data
rate. The received serial data passes through the receiver CDR, deserializer, word aligner, and rate matching
FIFO buffer. It is then looped back to the transmitter serializer and transmitted out through the transmitter
buffer. The received data is also available to the FPGA fabric through the port.
PCIe reverse parallel loopback mode is compliant with PCIe specification 2.1.
Cyclone V devices provide the
pipe_txdetectrx_loopback
input signal to enable this loopback
mode. If the
pipe_txdetectrx_loopback
signal is asserted in the P1 power state, receiver detection
is performed. If the signal is asserted in the P0 power state, reverse parallel loopback is performed.
Transceiver Protocol Configurations in Cyclone V Devices
Altera Corporation
CV-53004
Receiver Status
4-6
2013.10.17