Gating Off the CSR Clock in the RX LPI Mode
The following operations are performed when the MAC receives the LPI pattern from the PHY. †
1. The MAC RX enters the LPI mode and the RX LPI entry interrupt status [RLPIEN interrupt of Register
12 (
LPI_Control_Status
)] is set. †
2. The interrupt pin (
sbd_intr_o
) is asserted. The
sbd_intr_o
interrupt is cleared when the host
reads the Register 12 (
LPI_Control_Status
). †
After the
sbd_intr_o
interrupt is asserted and the MAC TX is also in the LPI mode, you can gate-off the
CSR clock. If the MAC TX is not in the LPI mode when you gate off the CSR clock, the events on the MAC
transmitter do not get reported or updated in the CSR. †
For restoring the CSR clock, wait for the LPI exit indication from the PHY after which the MAC asserts the
LPI exit interrupt on
lpi_intr_o
(synchronous to
clk_rx_i
). The
lpi_intr_o
interrupt is cleared
when Register 12 is read. †
Gating Off the CSR Clock in the TX LPI Mode
The following operations are performed when Bit 16 (LPIEN) of Register 12 (LPI Control and Status Register)
is set: †
1. The Transmit LPI Entry interrupt (TLPIEN bit of Register 12) is set. †
2. The interrupt pin (
sbd_intr_o
) is asserted. The
sbd_intr_o
interrupt is cleared when the host
reads the Register 12. †
After the
sbd_intr_o
interrupt is asserted and the MAC RX is also in the LPI mode, you can gate off the
CSR clock. If the MAC RX is not in the LPI mode when you gate off the CSR clock, the events on the MAC
receiver do not get reported or updated in the CSR. †
For restoring the CSR clock, switch on the CSR clock when the MAC has to come out of the TX LPI mode. †
After the CSR clock is resumed, reset Bit 16 (LPIEN) of Register 12 (LPI Control and Status Register) to
bring the MAC out of the LPI mode. †
Programming Guidelines for Flexible Pulse-Per-Second (PPS) Output
Generating Single Pulse on PPS
To generate single Pulse on PPS: †
1. Program 11 or 10 (for interrupt) in Bits [6:5], TRGTMODSEL, of Register 459 (PPS Control Register).
This instructs the MAC to use the Target Time registers (register 455 and 456) for start time of PPS signal
output. †
2. Program the start time value in the Target Time registers (register 455 and 456). †
3. Program the width of the PPS signal output in Register 473 (PPS0 Width Register). †
4. Program Bits [3:0], PPSCMD, of Register 459 (PPS Control Register) to 0001. This instructs the MAC
to generate single pulse on the PPS signal output at the time programmed in the Target Time registers
(register 455 and 456). †
Once the PPSCMD is executed (PPSCMD bits = 0), you can cancel the pulse generation by giving the Cancel
Start Command (PPSCMD=0011) before the programmed start time elapses. You can also program the
behavior of the next pulse in advance. To program the next pulse: †
Ethernet Media Access Controller
Altera Corporation
cv_54017
Gating Off the CSR Clock in the RX LPI Mode
17-56
2013.12.30
