Commands in DSR Application Subsystems
Timing Parameter Commands
194
Agilent 81250 Parallel Bit Error Ratio Tester, Programming Reference, March 2006
:PULSe:TRANsition[:LEADing]
Syntax
:<Handle>:SGENeral:
PDATa(*)
[:SOURce]:PULSe:TRANsition[:LEADing]
<LeadingEdge>
:<Handle>:SGENeral:
PDATa(*):TERMinal(*)
[:SOURce]:PULSe:TRANsition
[:LEADing] <LeadingEdge>
:<Handle>:SGENeral:
PPULse(*)
[:SOURce]:PULSe:TRANsition[:LEADing]
<LeadingEdge>
:<Handle>:SGENeral:
PPULse(*):TERMinal(*)
[:SOURce]:PULSe:TRANsition
[:LEADing] <LeadingEdge>
:<Handle>[:CGRoup(*)]:MODule(*):
CONNector(*)
[:SOURce]:PULSe:
TRANsition
[:LEADing] <LeadingEdge>
Parameters
<LeadingEdge>
Leading Edge value (<NRf>).
Sets the transition time for the LEADing edge. Only supported by
E4838A frontends. The valid ranges are
E4838A: 0.5ns … 5.0ns
Consider the following restrictions:
• When the specified port/terminal/connector is operating in NRZ
format-mode, the actual value range is restricted by the selected
period/frequency:
–
“:<Handle>:SGENeral:GLOBal:PERiod” on page 144
–
“:<Handle>:SGENeral:GLOBal:FREQuency” on page 145
–
“:MUX” on page 201
–
“:FORMat” on page 318
• When the specified port/terminal/connector is operating in RZ or
R1 format-mode, the actual value range is restricted by the selected
width or the duty cycle:
–
“:PULSe:WIDTh” on page 191
–
“:PULSe:DCYCle” on page 192
–
“:MUX” on page 201
–
“:FORMat” on page 318
Example
:_test:SGEN:PDAT1:PULS:TRAN 2e-9
:_test:SGEN:PDAT1:TERM1:SOUR:PULS:TRAN:LEAD
:_test:SGEN:PPUL1:PULS:TRAN 2e-9
:_test:SGEN:PPUL1:TERM1:SOUR:PULS:TRAN:LEAD 5e-9
:_test:MOD2:CONN3:PULS:TRAN 5e-9
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