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:SGENeral:GLOBal Subsystem
Commands in DSR Application Subsystems
Agilent 81250 Parallel Bit Error Ratio Tester, Programming Reference, March 2006
147
N O T E
For E4832A modules, the delay vernier and the functions for
automatic analyzer sampling delay adjustment require that the
minimum segment resolution of the desired system clock frequency is
used.
The E4861A module has a memory capacity of 8 MB per channel.
The E4861B module has a memory capacity of 16 MB per channel.
The E4866A and E4867A modules have a memory capacity of 32 MB
per channel.
System Clock
Frequency
Mbit/s
Segment
Resolution
bits
Memory
Depth
bits
Possible Frequency
Multipliers
337.500 – 675.000
16
2,097,152
1, 2, 4
≤
1,350.000
32
4,194,304
1/2, 1, 2
≤
2,700.000
64
8,388,608
1/4, 1/2, 1
System Clock
Frequency
(Mbit/s)
Segment
Resolution
(bits)
Memory
Depth
(bits)
Possible Frequency
Multipliers
20.834 to 41.666
1
131,072
1, 2, 4, 8, 16, 32, 64,
128
≤
82.333
2
262,144
1/2, 1, 2, 4, 8, 16, 32,
64
≤
166.666
4
524,288
1/4, 1/2, 1, 2, 4, 8, 16,
32
≤
333.333
8
1,048,576
1/8, 1/4, 1/2, 1, 2, 4, 8,
16
≤
666.666
16
2,097,152
1/16, 1/8, 1/4, 1/2, 1,
2, 4, 8
≤
1,333.333
32
4,194,304
1/32, 1/16, 1/8, 1/4,
1/2, 1, 2, 4
≤
2,700.000
64
8,388,608
1/64, 1/32, 1/16, 1/8,
1/4, 1/2, 1, 2
≤
3,350.000
128
16,777,216
1/128, 1/64, 1/32,
1/16, 1/8, 1/4, 1/2, 1
System Clock
Frequency
(Gbit/s)
Segment
Resolution
(bits)
Memory
Depth
(bits)
Possible Frequency
Multipliers
9.5 to 10.8
256
33,554,432
1
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