31.4.1.2 DDATA0 and DDATA1 Quick Observation
DDATA0LSBS in CRYPTO_DSTATUS shows the 4 least significant bits in DDATA0. DDATA0MSBS in CRYPTO_DSTATUS shows the 4
most significant bits of DDATA0, while DDATA1MSB in CRYPTO_DSTATUS shows the msb of DDATA1. These observation bitfields are
useful for determining the sign of the value in the data registers without having to read out the full register data register values
The 4 bits observed by DDATA0MSBS will change depending on RESULTWIDTH in CRYPTO_WAC. When using 260-bit results, DDA-
TA0MSBS shows bits 259-256, when using 256-bit results, it is bits 255-252, and for 128-bit results, bits 127-124 can be observed.
When RESULTWIDTH is 260 bits, the 4 most significant bits, e.g. bits 259-256 are also available in CRYPTO_DDATA0BYTE32, where
they can also be written. Using this register is the only way of inputting the upper 4 bits of a 260-bit number to CRYPTO.
31.4.1.3 Result Width
RESULTWIDTH in CRYPTO_WAC determines the width of the operation when performing arithmetic/shift instructions with CRYPTO.
Using less wide results will reduce the current consumption of the CRYPTO module. The higher-order bits that are beyond the selected
result width are ignored in the computation of arithmetic/shift operations, however, these higher-order bits will be undefined in the result
of such instructions.
When RESULTWIDTH=260BIT, all DDATA registers effectively become 260 bits wide, so that the upper 4 bits are not lost when trans-
ferring data from DDATA0 to the other DDATA registers. Likewise, the arithmetic/shift instructions shall consider the full 260-bit values
of DDATA0-DDATA4 when used as operation inputs. Note that DDATA0 is the only 260-bit register of which MSBs can be observed/
written. The upper 4 bits are observed through DDATA0MSBS in CRYPTO_DSTATUS or through CRYPTO_DDATA0BYTE32. For all
DDATAx registers, the extra MSBs are cleared when DDATAx is written. Furthermore, for a particular x, a write to DDATAx or any of its
aliased registers will cause DDATAx MSBs to be cleared. Note, writing to KEY/KEYBUF will only clear MSBs of DDATA1/DDATA4 when
AES256 mode is set. Likewise, writing to DATA0/DATA2 will not clear DDATA2/DDATA3 MSBs.
Since the DATA0-DATA3 registers are always 128-bit, all bit positions greater than 128 are interpreted as 0 when RESULTWIDTH is
greater than 128 bits. However, the assignment instructions DATAxTODDATAy will not zero-out the upper 128 bits of the DDATAy tar-
get. Instead, those upper words become undefined after such operations.
31.4.2 Instructions and Execution
The CRYPTO module implements a set of instructions in order to load and manipulate data effectively. These instructions are grouped
into four types:
• ALU instructions - arithmetic and logical bitwise operations
• Transfer instructions - moving data between registers and external peripherals like DMA and the BUFC
• Conditional instructions - conditionally execute instructions based on context
• Special instructions - various crypto and support instructions
A single instruction can be executed by writing INSTR in CRYPTO_CMD. This will execute the instruction, and the interface of CRYP-
TO will be locked until the execution has completed. Multiple commands can safely be issued after each other by the CPU as long as
NOBUSYSTALL in CRYPTO_CTRL is not set. If CRYPTO gets a new command or a data access request while busy it will then stall the
bus, and execute the new command as soon as it is done with the previous one. Note, there are some exceptions to this rule. For
example, see
.
Stalling of the bus can be disabled by setting NOBUSYSTALL in CRYPTO_CTRL, however manipulating (reading or writing) registers
while running an instruction will result in undefined behaviour. Additionally, if NOBUSYSTALL=0 and a new command or data access
request is made while the CRYPTO is simultaneously performing a data transfer instruction, it is possible for system lockup due to bus
stalling loops. The safest approach is to always check if an instruction is running by looking at INSTRRUNNING in CRYPTO_STATUS.
Note that this automatic stalling feature does not apply to automated CRYPTO instruction sequences (described next), since there may
be cycle delays between individual instructions for which bus accesses are not prevented. For sequences, always check the SEQRUN-
NING status bit or the SEQDONE interrupt flag to ensure the sequence is finished before attempting CRYPTO register accesses.
Reference Manual
CRYPTO - Crypto Accelerator
silabs.com
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