31.4.1 Data and Key Registers
The CRYPTO module contains five 256-bit registers. Accelerators are implemented through instructions operating on these registers,
either by copying data between registers and external components like the BUFC or through DMA, or by executing instructions on the
registers.
Depending on the instruction, the registers can be accessed as 128-bit, 256-bit or 512-bit registers. The registers can also be accessed
through different interface registers to achieve different results.
When writing to and reading from the CRYPTO_DATAx, CRYPTO_KEY, CRYPTO_KEYBUF, CRYPTO_DDATAx and CRYPTO_QDA-
TAx registers, the least significant part is accessed first and the most significant part last, see
Figure 31.2 CRYPTO Data and Key Reg-
. The same is the case for the XOR and byte-access registers for DATA0 and DATA1. It is important to
note that some of the 256-bit registers are composed of the 128-bit registers, and both the 512-bit registers are composed of the 256-bit
registers.
Note:
From here on, the 128, 256 and 512-bit registers are named DATAx, DDATAx, QDATAx, etc, And the access-points to these reg-
isters are named CRYPTO_DATAx, CRYPTO_DDATAx, CRYPTO_QDATAx, etc.
DATA0 can be accessed through CRYPTO_DATA0 (32-bit), CRYPTO_DATA0XOR (32-bit), CRYPTO_DATA0BYTE (8-bit) and CRYP-
TO_DATA0XORBYTE (8-bit). Direct access to bytes 12 - 15 is available through CRYPTO_DATA0BYTE12-15 (8-bit). The DATA0XOR
(in CRYPTO_DATA0XOR) is used for XOR'ing a value with the current value in DATA0. This is used in a large variety of block cipher
modes. All of these registers operate on DATA0.
DATA1 can be accessed through CRYPTO_DATA1 (32-bit) and CRYPTO_DATA1BYTE (8-bit).
The remaining data registers have regular 32-bit access through their respective registers. Note that all data registers require a full read
or write to be fully accessed. This means that the 128-bit registers need four 32-bit reads/writes, the 256-bit registers need 8 reads/
writes and the 512-bit registers need 16 reads/writes. For a read, if all read accesses are not done, the register will end up as a shifted
version of the original value.
Note:
For byte-wise data accesses (DDATAxBYTE, DATAxBYTE, etc.), all reads and writes must be performed in groups of 4, due to
internal buffering and shifting of 32 bits at a time. Accessing a number of bytes that is not a multiple of four can cause data incoherency
in all of the data registers.
The KEY and KEYBUF registers are 256 bit wide when AES256 is set in CRYPTO_CTRL. Else they are 128 bit wide. When used as a
part of DDATAx and QDATAx, they are always 256 bit wide.
The registers DDATA0BIG and QDATA1BIG produce byte-swapped versions of DDATA0 and QDATA1 respectively. These may be used
when a computation requires byte-swapping. An example of this is SHA computation, where data needs to be changed to big endian
before CRYPTO can work with it. Little endian data is then loaded in through QDATA1BIG and the resulting little endian hash can be
read out from DDATA0BIG, see
Except for KEYBUF, the contents of all data registers are lost when going to EM2.
Reference Manual
CRYPTO - Crypto Accelerator
silabs.com
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