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even while the system is running on the HFRCO. Only write CMU_HFRCOCTRL when it is ready for an update as indicated by
HFRCOBSY=0 in CMU_SYNCBUSY.
Offset
Bit Position
0x010
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0xB
0
0x0
1
0x2
0x08
0x1F
0x7F
Access
R
WH
R
WH
R
WH
R
WH
R
WH
R
WH
R
WH
R
WH
Name
Bit
Name
Reset
Access Description
31:28
VREFTC
0xB
RWH
HFRCO Temperature Coefficient Trim on Comparator Reference
Writing this field adjusts the temperature coefficient trim on comparator reference.
27
FINETUNINGEN
0
RWH
Enable Reference for Fine Tuning
Settings this bit enables HFRCO fine tuning.
26:25
CLKDIV
0x0
RWH
Locally Divide HFRCO Clock Output
Writing this field configures the HFRCO clock output divider.
Value
Mode
Description
0
DIV1
Divide by 1.
1
DIV2
Divide by 2.
2
DIV4
Divide by 4.
24
LDOHP
1
RWH
HFRCO LDO High Power Mode
Settings this bit puts the HFRCO LDO in high power mode.
23:21
CMPBIAS
0x2
RWH
HFRCO Comparator Bias Current
Writing this field adjusts the HFRCO comparator bias current.
20:16
FREQRANGE
0x08
RWH
HFRCO Frequency Range
Writing this field adjusts the HFRCO frequency range.
15:14
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
13:8
FINETUNING
0x1F
RWH
HFRCO Fine Tuning Value
Writing this field adjusts the HFRCO fine tuning value. Higher value means lower frequency. Fine tuning is only enabled
when FINETUNINGEN is set.
7
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
6:0
TUNING
0x7F
RWH
HFRCO Tuning Value
Writing this field adjusts the HFRCO tuning value. Higher value means lower frequency.
Reference Manual
CMU - Clock Management Unit
silabs.com
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