
31.6 Register Description
31.6.1 CRYPTO_CTRL - Control Register
Offset
Bit Position
0x000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0x0
0x0
0x0
0x0
0x0
0
0
0
0
Access
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
Name
Bit
Name
Reset
Access Description
31
COMBDMA0WEREQ 0
RW
Combined Data0 Write DMA Request
When cleared, the DATA0WR and DATA0XORWR operate independently. When set, DATA0XORWR requests are also giv-
en through DATA0WR
30
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
29:28
DMA1RSEL
0x0
RW
DATA0 DMA Unaligned Read Register Select
Specifies which read register is used for DMA1RD DMA requests (see related notes in
Value
Mode
Description
0
DATA1
1
DDATA1
2
QDATA1
3
QDATA1BIG
27:26
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
25:24
DMA1MODE
0x0
RW
DMA1 Read Mode
This field determines how data is read when using DMA
Value
Mode
Description
0
FULL
Target register is fully read/written during every DMA transaction
1
LENLIMIT
Length Limited. When the current length, i.e. LENGTHA or LENGTHB
indicates that there are less bytes available than the register size, only
1 bytes + necessary zero padding is read. Zero padding is au-
tomatically added when writing.
2
FULLBYTE
Target register is fully read/written during every DMA transaction. Byte-
wise DMA.
Reference Manual
CRYPTO - Crypto Accelerator
silabs.com
| Building a more connected world.
Rev. 1.1 | 1046