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12. SMU - Security Management Unit
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Quick Facts
What?
The Security Management Unit (SMU) forms the
control and status/reporting component of bus-level
security in the EFR32.
Why?
Enables a robust and low-energy security solution at
the system level
How?
Hardware context switching and access control pro-
vided via BLS components.
12.1 Introduction
The Security Management Unit (SMU) peripheral adds hardware access control over all of the MCU peripherals that are managed by
low level firmware integrated into a Real Timer Operating System (RTOS). The SMU is used in conjuntion with the Cortex-M operating
modes (privileged and non-privileged) and the Memory Protection Unit (MPU). The EFR32 MCUs include the ARM v7-M MPU that de-
fines configurable access parameters to regions within the entire CPU memory map. The MPU is not covered in detail in this reference
manual. For a complete description of the MPU registers etc, consult the ARM v7-M Architecture Reference Manual. The MPU can
define up to 8 regions of varying sizes within the memory map, with each region also being able to be split into 8 equal sub-regions.
Using these regions, firmware can define rules that enforce privileged and non-privileged accesses to different memory locations. For
example, sections of flash can be marked as priviliged access, whereas other areas within the flash can be marked as having non-
privileged mode acess. Only privileged mode regions can access other privileged mode regions. Accesses attempted by a non-privi-
leged region to a privileged region will cause a fault. The access permissions can be extended across the entire memory map including
the peripheral region.
The Cortex-M starts up in privileged mode and the MPU is disabled after reset which means all regions in the memory map are access-
ble to the running application code. For many applications this is sufficient and the MPU remains disabled. However, when using a
RTOS the kernel requires protection from user code and will switch to privileged mode and create tasks in non-privileged or thread
mode. In addition, security is also a concern, so MCU peripherals should be protected to avoid security holes. Adding peripheral securi-
ty to systems requires an increased number of MPU regions to protect areas such as the peripheral registers, including bit set/clear and
bit banding regions. The defined regions are also dynamic based on the task requirements and in many cases the number of regions
required exceeds the number of regions that can be enabled by the MPU.
The SMU is used to extend the access controls of each peripheral beyond the number of regions available using the MPU. The SMU
peripheral registers provide the configuration and status bits for the Peripheral Protection Unit (PPU) to the CPU. The PPU is the under-
lying hardware component that operates on the low level bus interfaces within the SoC to derive the status for each peripheral .
12.2 Features
The main features of the SMU are as follows:
• Contains control and status registers for hardware bus level component instances (e.g., the PPU)
• Simplifies RTOS context switching
• Hardware to complement any software context switching enabled by an MPU
• Hardware-enforced access control extends capability of the v7-M MPU regions
• One bit control per peripheral reduces software overhead while dynamically modifying access permissions
• A configurable interrupt line that can be triggered from peripheral access fault events
Reference Manual
SMU - Security Management Unit
silabs.com
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