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20.5.15 TIMERn_CCx_CTRL - CC Channel Control Register
Offset
Bit Position
0x060
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0x0
0x0
0x0
0x0
0x0
0x0
0
0
0x0
Access
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
Name
Bit
Name
Reset
Access Description
31
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
30
FILT
0
RW
Digital Filter
Enable digital filter.
Value
Mode
Description
0
DISABLE
Digital filter disabled
1
ENABLE
Digital filter enabled
29
INSEL
0
RW
Input Selection
Select Compare/Capture channel input.
Value
Mode
Description
0
PIN
TIMERnCCx pin is selected
1
PRS
PRS input (selected by PRSSEL) is selected
28
PRSCONF
0
RW
PRS Configuration
Select PRS pulse or level.
Value
Mode
Description
0
PULSE
Each CC event will generate a one HFPERCLK cycle high pulse
1
LEVEL
The PRS channel will follow CC out
27:26
ICEVCTRL
0x0
RW
Input Capture Event Control
These bits control when a Compare/Capture PRS output pulse and interrupt flag is set. DMA request however is set on
every capture.
Value
Mode
Description
0
EVERYEDGE
PRS output pulse and interrupt flag set on every capture
1
EVERYSECONDEDGE PRS output pulse and interrupt flag set on every second capture
2
RISING
PRS output pulse and interrupt flag set on rising edge only (if ICEDGE
= BOTH)
3
FALLING
PRS output pulse and interrupt flag set on falling edge only (if ICEDGE
= BOTH)
Reference Manual
TIMER/WTIMER - Timer/Counter
silabs.com
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