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4.7.44 DCDCLPCMPHYSSEL1 - DCDC LPCMPHYSSEL Trim Register 1
Offset
Bit Position
0x180
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
RO
RO
RO
RO
Name
Bit
Name
Access
Description
31:24
LPCMPHYSSELLPCMPBIAS3
RO
DCDC LPCMPHYSSEL Trim, LPCMPBIAS=3
23:16
LPCMPHYSSELLPCMPBIAS2
RO
DCDC LPCMPHYSSEL Trim, LPCMPBIAS=2
15:8
LPCMPHYSSELLPCMPBIAS1
RO
DCDC LPCMPHYSSEL Trim, LPCMPBIAS=1
7:0
LPCMPHYSSELLPCMPBIAS0
RO
DCDC LPCMPHYSSEL Trim, LPCMPBIAS=0
Reference Manual
Memory and Bus System
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