Schweitzer Engineering SEL-387-0, Instruction Manual

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9.13
Date Code 20170601 Instruction Manual SEL-387-0, -5, -6 Relay
Event Reports and SER
Standard 15-, 30-, or 60-Cycle Event Reports
Set 1
V1
V2
V3
V4 p
T
d
S1V n asserted (timing to output)
S1V n T asserted (timed out); S1V n asserted
S1V n T asserted, S1V n deasserted (timing to reset)
Set 1
LT 12 1
2
b
Latch Bit 1 Latched
Latch Bit 2 Latched
Latch Bit 1 and Latch Bit 2 Latched
Set 1
LT 34 3
4
b
Latch Bit 3 Latched
Latch Bit 4 Latched
Latch Bit 3 and Latch Bit 4 Latched
Set 2
V1
V2
V3
V4 p
T
d
S2V n asserted (timing to output)
S2V n T asserted (timed out); S2V n asserted
S2V n T asserted, S2V n deasserted (timing to reset)
Set 2
LT 12 1
2
b
Latch Bit 1 Latched
Latch Bit 2 Latched
Latch Bit 1 and Latch Bit 2 Latched
Set 2
LT 34 3
4
b
Latch Bit 3 Latched
Latch Bit 4 Latched
Latch Bit 3 and Latch Bit 4 Latched
Set 3
V1
V2
V3
V4
V5
V6
V7
V8
p
T
d
S3V n asserted (timing to output)
S3V n T asserted (timed out); S3V n asserted
S3V n T asserted, S3V n deasserted (timing to reset)
RB 12 1
2
b
RB1 asserted
RB2 asserted
RB1 and RB2 asserted
RB 34 3
4
b RB3 asserted
RB4 asserted
RB3 and RB4 asserted
RB 56 5
6
b RB5 asserted
RB6 asserted
RB5 and RB6 asserted
RB 78 7
8
b RB7 asserted
RB8 asserted
RB7 and RB8 asserted
OUT 12 1
2
b OUT101
asserted
OUT102
asserted
OUT101
and
OUT102
asserted
OUT 34 3
4
b
OUT103 asserted
OUT104
asserted
OUT103
and
OUT104
asserted
OUT 56 5
6
b OUT105 asserted
OUT106 asserted
OUT105 and OUT106 asserted
OUT 7A 7
A
b OUT107 asserted
ALARM asserted
OUT107 and ALARM asserted
Table 9.6 Differential Event Report Element Columns (Sheet 2 of 3)
Column
Heading
Symbol Definition