IC-Module for EtherNet/IP
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to "high" and the Master can start transmission of the block
immediately. A maximum delay between setting the CS signal and
releasing by the ready signal of the module is 10 ms. All bytes of a
data block are now transmitted directly in succession at the rate
preset by the Master. After the last bit of the data block has been
transmitted, the Master indicates the end of the transmission by
resetting the SPI Chip Select line to "low". The module responds to
this by resetting the SPI Ready line to "low". This happens at the
earliest, however (maximum 10 ms after resetting CS), when the
data has been processed insofar as the status was determined and
is ready in the SPI output buffer so that the next transmission can
start. This must first be requested, however, by the Master (as
described above) by setting the SPI Chip Select line to "high".
Chip Select
(Master)
Ready
(Slave)
Data
(Master & Slave)
Protocol
KUNBUS has defined a separate protocol for the data exchange via
the synchronous serial interface. This protocol allows you to perform
various read and write access operations. Here, the Master first
always sends a transmission block with 5 bytes. The first 3 to 5 bytes
of this transmission block consist of meta data (target address, etc.).
Depending on the access type, another transmission block of
variable data length follows the first block. Write and read access to
the memory register of the module is performed. Only memory
registers that have been enabled can be written or read, of course.
The following areas cannot be written:
Input data areas:
– Fieldbus
– SDI
Output data areas:
– Fieldbus
– SSC
– SDI
When writing to the SSC input data area, the time monitoring is reset
for this area (see Valid Time, Section "Data Broker [
}
14]").
The various access types are explained below.
Components
