IC-Module for EtherNet/IP
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Operating mode as SPI Slave
NOTICE
The names SSC input and SSC output are defined from the data
brokers point of view. If the SPI master wants to read data from the IC
module, it must read data from the SSC output area from address
0x2001 onwards. It must write data to the SSC input area from
address 0x1001.
In SPI Slave mode, the transmission of the process data between an
SPI Master and the SSC Input or Output registers takes place in data
blocks, which, in addition to the actual process data, also contain
metadata (e.g. for indicating the register addresses for source and
target areas). Such data blocks are transmitted with a hardware
handshake. The actual data transmission lines MOSI, MISO and
Clock are used with 3.3 V logic in the usual manner. Here, you can
freely select the normally alterable parameters CPOL (Clock polarity)
and CPHA (Clock Phase) in KUNBUS-IC and define these
permanently via the CDI Menu [
}
104] or memory register [
}
68].
The bit sequence (MSB first or MSB last) is fixed for IC modules, the
module always starts the transmission with the MSB (bit of highest
value) of a byte. All bytes belonging to a block are transmitted in a
continuous sequence.
The clock signal required is generated externally from the Master.
The KUNBUS-IC can process maximum clock frequencies of
20 MHz.
NOTICE
The addresses described start at 1, while the addresses in the data
blocks start at 0.
Keep this in mind when configuring. Always subtract 1 from the value
described here.
For example, if the first register of the SSC output register area with the
address 0x2001 is to be read, address 0x2000 must be transferred in the
data block.
Handshaking
The handshaking lines ensure that a Master first sends the
subsequent transmission block after the module has processed the
block that was received previously.
The module indicates by the "low" level on the SPI ready line that a
transmission cycle has been completed, the status of the last
transmission is waiting to be retrieved and the Master can trigger the
next cycle. The Master starts this cycle by setting the SSC Chip
Select line to "high" to indicate to the module that data is ready for
transmission and the following data block is meant for the module
(theoretically, a master can address several modules). Once the
module is ready for this data transmission, it sets the SPI ready line
Components
