JDS Uniphase CellAdvisor JD780A Series, User Manual

Page: 534 / 592

JD780A Series Analyzers
534
Using T1 Analyzer
Performing loop testing
Making a test
Procedure
To select the measurement mode:
1.
Press the MODE hard key.
2.
Press the E1/T1 Analyzer soft key.
3.
Select T1 Analyzer > Loop Test .
To configure measurement parameters:
1.
Press the MEASURE SETUP hot key.
2.
Press the RX Mode soft key, and then select the receiver input option from the following choices:
–
Terminate: Provides 100-ohm nominal input impedance, according to the framing, line
code, and BER pattern settings.
–
Bridge: Provides input impedance greater than one kilohm for in-service monitoring,
bridging the receiver input across lines that are terminated elsewhere in the network.
–
Monitor: Provides 100-ohm nominal input impedance for the in-service monitoring of T1
lines.
3.
Toggle the Framing soft key between SF-D4 and ESF and select the framing type for your
receiver setting:
–
SF-D4 (Super Frame-D4): Group of 12 frames, used to align equipment for framing.
–
ESF (Extended Super Frame): Group of 24 frames, used to align equipment for framing.
4K for a maintenance channel (Facilities Data Link), 2K for CRC-6 checksum, and 2K for
framing/synchronization.
NOTE
If the framing type does not match with your receiver setting, a framing alarm occurs.
4.
Toggle the Line Code soft key between AMI and B8ZS and select the line code type to send an
T1 signal:
–
AMI: It stands for Alternate Mark Inversion. A line code uses one three level signal to
convey binary digits in which successive binary ones (
“marks” or pulses) are of alternating
polarity, either positive or negative, equal in amplitude. A binary zero
(“space”) is
transmitted as no pulse or zero amplitude.
–
B8ZS: It stands for Bipolar with 8-Zero Substitution. A coding scheme in which the
transmitter "substitutes" a fixed pattern of ones, zeros, and BPVs in place of 8 consecutive
zeros.
5.
Press the Pattern soft key, and then select the stress pattern option from the following choices:
–
1-8: An eight-bit pattern that contains a single one, being used to test clock recovery.
–
1-16: A sixteen-bit pattern that contains a single one, being used to test clock recovery.
–
All 1
’S:
A pattern that causes line drivers to consume the maximum power.
–
All 0
’S:
A pattern that is often selected to verify HDB3 provisioning. Circuit will drop if
optioned for AMI.
–
Alternate: A pattern that alternates between ones and zeroes.
–
3-24: A twenty-four bit-pattern containing 3 ones with the longest length of consecutive
zeroes constrained to fifteen. It has ones density of 12.5% and is used to check clock
recovery.
–
QRSS: A pseudorandom pattern that is a common test pattern and simulates live traffic on
a circuit.