CMT2380F17
Rev0.1 | 164/347
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16.3.9
Split Timer 3 Mode 4 (8-bit PWM Mode)
In this mode, Timer 3 is an 8-bit PWM mode as shown in Figure 16
–35. TH3 and RCAP3H are combined
to an 8-bit auto-reload counter. Software configures these two registers to decide the PWM cycle time. TL3 is
the PWM compare register to generate PWM waveform. RCAP3L is the PWM buffer register and software will
update PWM data in this register. Each TH3 overflow event will set TF3 and load RCAP3L value into TL3. The
PWM signal will be output on T3CKO function pin and the output is gated by T3OE in T3MOD register.
Figure 16-35. Split Timer 3 Mode 4 Structure (8-bit PWM mode)
16.3.10
Timer 3 Programmable Clock Output
Timer 3 has a Clock-Out Mode (while CP/RL3=0 & T3OE=1). In this mode, Timer 3 operates as a
programmable clock generator with 50% duty-cycle. The generated clocks come out on T3CKO port pin. The
input clock (SYSCLK/2 or SYSCLK) increments the 16-bit timer (TH3, TL3). The timer repeatedly counts to
overflow from a loaded value. Once overflows occur, the contents of (RCAP3H, RCAP3L) are loaded into
(TH3, TL3) for the consecutive counting. Figure 16
–32 gives the formula of Timer 3 clock-out frequency:
Figure 16
–37 shows the clock structure of Timer 3.
Figure 16-36. Timer 3 clock out equation
Note:
(1) Timer 3 overflow flag, TF3, will be set when Timer 3 overflows to generate interrupt. But, the TF3
interrupt can be blocked by TF3IG in T3MOD1 register.
Summary of Contents for CMT2380F17
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Page 177: ...CMT2380F17 Rev0 1 177 347 www cmostek com Figure 17 3 PCA Interrupt System...
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