CMT2380F17
Rev0.1 | 145/347
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16.2.5
Split Timer 2 Mode 0 (AR and Ex. INT)
When T2SPL is set in this mode, Timer 2 operates as two 8-bit timers (TH2 and TL2). Both 8-bit timers
operate in up-counter as shown in Figure 16
–16. TH2 holds the reload value for RCAP2H and keep the same
8 clock source
inputs selection as 16-bit mode. It behaves the 8-bit function liked Timer 2 Mode 0 in 16-bit mode. TL2
holds the reload value for RCAP2L with 4 clock inputs selection. The TR2 bit in T2CON handles the run
control for TH2. The TR2L bit in T2MOD handles the run control for TL2. And TH2 overflow can stop the TR2L
running when TR2LC is set.
There are 3 interrupt flags in split mode, EXF2, TF2 and TF2L. EXF2 has the same function as 16-bit
mode to detect the transition on T2EXI. TF2 is set when TH2 overflows from 0xFF to 0x00 with TF2IG control.
TF2L is set when TL2 overflows from 0xFF to 0x00 with interrupt enabled by TL2IE. The EXF2, TF2 and TF2L
interrupt flags are not cleared by hardware and must be cleared by software.
By the way, the Timer 2 overflow event (T2OF) in 16-bit timer is replaced by TL2 overflow event (TL2OF)
in this split mode.
If TL2IS in T2MOD1 is 0, the bits on T2CON.5~4 are the function of RCLK and TCLK. If TL2IS is 1, the
bits on T2CON.5~4 are the function of TF2L and TL2IE.
Figure 16-16. Split Timer 2 Mode 0 Structure (AR and Ex. INT)
Summary of Contents for CMT2380F17
Page 27: ...CMT2380F17 Rev0 1 27 347 www cmostek com 1 25 Phase Noise...
Page 177: ...CMT2380F17 Rev0 1 177 347 www cmostek com Figure 17 3 PCA Interrupt System...
Page 246: ...CMT2380F17 Rev0 1 246 347 www cmostek com SnMIPS S0MI S1MI 1 P3 3 P4 7...
