CMOSTEK CMT2380F17, Manual

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CMT2380F17
Rev0.1 | 79/347
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ECKI (P6.0)
(0,0,0)
RTCPS[0:4] RTCPS[5:8]
RTC Prescaleer
ILRCO
(0,0,1)
WDTPS
(0,1,0)
WDTOF
(0,1,1)
SYSCLK
(1,0,0)
SYSCLK/12
(1,0,1)
RTCPS[9:12]
32 16
0
RTCPS[13:14]
16
1 0
15
4
(/2^15)
RTCPS[14]
(0,0,0,0)
RTCPS[13]
(0,0,0,1)
RTCPS[12]
(0,0,1,0)
RTCPS[11]
(0,0,1,1)
RTCPS[10]
(0,1,0,0)
1 0
15
1
3
RCSS[2:0]
RPCS[0] RPCS[1] RPCS[2]
RTCPS[1]
(1,1,0,1)
RTCPS[0]
(1,1,1,0)
RTCPSI
(1,1,1,1)
RTCCS[3:0]
RCSS[2:0] RPSC[2:0] RTCCS[3:2]
CKCON4 Register
Reload
EIE1.ESF
SFIE.RTCFIE
RTCCS[1:0] RTCCT[5:0]
RTC
Interrupt
RTCTM Register
RTCCT[5:0]
6-bit Counter
Over flow
RTCF
PCON1.4
SFR P4.5
Toggle
RTCCR Register
RTCE
RT CO
0
1
RTCKO
D Q
RTCRL[5:0]
RTCRL[5:0]
Figure 11-1. Real-Time-Clock Counter

RTCCR : Real-Time-Clock Control Register
SFR Page = 0~7 & P
SFR Address = 0xBE/0x54
Bit 7 6 5 4 3 2 1 0
Name RTCE RTCO RTCRL[5:0]
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset Value
0 0 1 1 1 1 1 1
Bit 7: RTCE, RTC Enable.
0: Stop RTC Counter, RTCCT.
1: Enable RTC Counter and set RTCF when RTCCT overflows. When RTCE is set, CPU can not access
RTCTM. RTCTM must be accessed in RTCE cleared.
Bit 6: RTCO, RTC Output enabled. The frequency of RTCKO is (RTC overflow rate)/2. 0: Disable the
RTCKO output.
1: Enable the RTCKO output on P4.5.
Bit 5~0: RTCRL[5:0], RTC counter reload value register. This register is accessed by CPU and the
content in the register is reloaded to RTCCT when RTCCT overflows.

RTCTM : Real-Time-Clock Timer Register
SFR Page = 0~7 & P
SFR Address = 0xB6/0x55
Bit 7 6 5 4 3 2 1 0
Name RTCCS[1:0] RTCCT[5:0]
R/W R/W R/W R/W R/W R/W R/W R/W R/W