CMOSTEK CMT2380F17, Manual

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CMT2380F17
Rev0.1 | 120/347
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15.7 Interrupt Register

TCON
：
Timer/Counter Control Register
SFR Page = 0~F
SFR Address = 0x88
Bit
7 6 5 4 3 2 1 0
Name
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset Value 0 0 0 0 0 0 0 0
Bit 3: IE1, Interrupt 1 (nINT1) Edge flag.
0: Cleared when interrupt processed on if transition-activated.
1: Set by hardware when external interrupt 1 (nINT1) edge is detected (transmitted or level-activated).
Bit 2: IT1: Interrupt 1 (nINT1) Type control bit.
0: Cleared by software to specify low level triggered external interrupt 1 (nINT1). If INT1H (AUXR0.1) is
set, this bit specifies high level triggered on nINT1.
1: Set by software to specify falling edge triggered external interrupt 1 (nINT1). If INT1H (AUXR0.1) is set,
this bit specifies rising edge triggered on nINT1.
Bit 1: IE0, Interrupt 0 (nINT0) Edge flag.
0: Cleared when interrupt processed on if transition-activated.
1: Set by hardware when external interrupt 0 (nINT0) edge is detected (transmitted or level-activated).
Bit 0: IT0: Interrupt 0 (nINT0) Type control bit.
0: Cleared by software to specify low level triggered external interrupt 0 (nINT0). If INT0H (AUXR0.0) is
set, this bit specifies high level triggered on nINT0.
1: Set by software to specify falling edge triggered external interrupt 0 (nINT0). If INT0H (AUXR0.0) is set,
this bit specifies rising edge triggered on nINT0.

IE
：
Interrupt Enable Register
SFR Page = 0~F
SFR Address = 0xA8
Bit 7 6 5 4 3 2 1 0
Name EA EDMA ET2 ES0 ET1 EX1 ET0 EX0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset Value 0 0 0 0 0 0 0 0