CMT2380F17
Rev0.1 | 260/347
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21.1.2
Master Receiver Mode
In the master receiver mode, a number of data bytes are received from a slave transmitter. SICON must
be initialized as in the master transmitter mode. When the start condition has been transmitted, the interrupt
service routine must load SIDAT with the 7-bit slave address and the data direction bit (SLA+R). The SI bit in
SICON must then be cleared before the serial transfer can continue.
When the slave address and the data direction bit have been transmitted and an acknowledgment bit has
been received, the serial interrupt flag (SI) is set again, and a number of status codes in SISTA are possible.
They are 40H, 48H, or 38H for the master mode and also 68H, 78H, or B0H if the slave mode was enabled
(AA=1). The appropriate action to be taken for each of these status codes is detailed in the following operating
flow chart. After a repeated start condition (state 10H), TWI/ I2C may switch to the master transmitter mode by
loading SIDAT with SLA+W.
21.1.3
Slave Transmitter Mode
In the slave transmitter mode, a number of data bytes are transmitted to a master receiver. To initiate the
slave transmitter mode, SIADR and SICON must be loaded as follows:
SIADR
Bit
7
6
5
4
3
2
1
0
Name
A6
A5
A4
A3
A2
A1
A0
GC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
0
0
0
0
0
X
0
0
|<--------------------------------------------- Own Slave Address -------------------------------------------->|
The upper 7 bits are the address to which TWI/ I2C will respond when addressed by a master. If the LSB
(GC) is set, TWI/ I2C will respond to the general call address (00H); otherwise it ignores the general call
address.
SICON
Bit
7
6
5
4
3
2
1
0
Name
CR2
ENSI
STA
STO
SI
AA
CR1
CR0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
X
1
0
0
0
1
X
X
CR0, CR1, and CR2 do not affect TWI/ I2C in the slave mode. ENSI must be set to “1” to enable TWI/ I2C.
The AA bit must be set to enable TWI/ I2C to acknowledge its own slave address or the general call address.
STA, STO, and SI must be cleared to “0”.
When SIADR and SICON have been initialized, TWI/ I2C waits until it is addressed by its own slave
address followed by the data
direction bit which must be “1” (R) for TWI/ I2C to operate in the slave transmitter
mode. After its own slave address and the “R
”
bit have been received, the serial interrupt flag (SI) is set and
a valid status code can be read from SISTA. This status code is used to vector to an interrupt service routine,
and the appropriate action to be taken for each of these status codes is detailed in the following operating flow
chart. The slave transmitter mode may also be entered if arbitration is lost while TWI/ I2C is in the master
mode (see state B0H).
If the AA bit is reset during a transfer, TWI/ I2C will transmit the last byte of the transfer and enter state
C0H or C8H. TWI/ I2C is switched to the not-addressed slave mode and will ignore the master receiver if it
continues the transfer. Thus the master receiver receives all 1s as serial data. While AA is reset, TWI/ I2C
does not respond to its own slave address or a general call address. However, the serial bus is still monitored,
Summary of Contents for CMT2380F17
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