CMT2380F17
Rev0.1 | 279/347
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25 General Purpose Logic (GPL-CRC)
The CMT2380F17 builds in a general purpose logic cyclic redundancy check function with CCITT16
(CRC16 0x1021) polynomial. The CRC accepts a stream of 8-bit data written to the CRC0DI. Its initial value
(seed value) is programmable for multi-purpose applications. The 16-bit initial value (seed value) is set to high
byte CRC0SH (CRCDS0~1=01) and low byte CRC0SL (CRCDS0~1=00). The result is stored in CRC0RH
(CRCDS0~1=01) and CRC0RL (CRCDS0~1=00).
The GPL-CRC has another data path direct from Flash memory by the Flash Auto-Reload Engine to
dynamically check the data correctness in the Flash.
The GPL-CRC can also combine the data inverse function. To write the data byte into BOREV register
and it will be flipped automatically when read it back from BOREV. The MSB becomes the LSB.
。
25.1
GPL-CRC Structure
In the normal mode, it needs to set the seed in CRC0SH and CRC0SL and then write the data into
CRC0DI to start the conversion.
In the Flash Auto-
Reload mode, it needs to keep CRCDS1~0 at “0x11”. And follow the steps show in
below:
：
1.
To set the start address of the reload sector, this is defined in IFADRH and IFADRL.
2.
To set its end-address is combined the IAPLB (7 bits)
and 9’b1-1111-1111.
3.
Set IFMT register (ISP/IAP Flash Mode) to 0x80 for Flash Auto-Reload mode.
4.
Sequentially write 0x46h then 0xB9h to SCMD register to trigger CRC calculation.
Figure 25
–1. CRC structure
Summary of Contents for CMT2380F17
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