CMOSTEK CMT2380F17, Manual

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CMT2380F17
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20.2.1 Additional Considerations for a Slave
When CPHA is 0, SSIG must be 0 and nSS pin must be negated and reasserted between each
successive serial byte transfer. Note the SPDAT register cannot be written while nSS pin is active (low), and
the operation is undefined if CPHA is 0 and SSIG is 1.
When CPHA is 1, SSIG may be 0 or 1. If SSIG=0, the nSS pin may remain active low between
successive transfers (can be tied low at all times). This format is sometimes preferred for use in systems
having a single fixed master and a single slave configuration.
20.2.2 Additional Considerations for a Master
In SPI, transfers are always initiated by the master. If the SPI is enabled (SPEN=1) and selected as
master, writing to the SPI data register (SPDAT) by the master starts the SPI clock generator and data transfer.
The data will start to appear on MOSI about one half SPI bit-time to one SPI bit-time after data is written to
SPDAT.
Before starting the transfer, the master may select a slave by driving the nSS pin of the corresponding
device low. Data written to the SPDAT register of the master is shifted out of MOSI pin of the master to the
MOSI pin of the slave. And, at the same time the data in SPDAT register of the selected slave is shifted out on
MISO pin to the MISO pin of the master.
After shifting one byte, the SPI clock generator stops, setting the transfer completion flag (SPIF) and an
interrupt will be created if the SPI interrupt is enabled. The two shift registers in the master CPU and slave
CPU can be considered as one distributed 16-bit circular shift register. When data is shifted from the master to
the slave, data is also shifted in the opposite direction simultaneously. This means that during one shift cycle,
data in the master and the slave are interchanged.
20.2.3 Mode Change on nSS-pin
If SPEN=1, SSIG=0, MSTR=1 and /SS pin=1, the SPI is enabled in master mode. In this case, another
master can drive this pin low to select this device as an SPI slave and start sending data to it. To avoid bus
contention, the SPI becomes a slave. As a result of the SPI becoming a slave, the MOSI and SPICLK pins are
forced to be an input and MISO becomes an output. The SPIF flag in SPSTAT is set, and if the SPI interrupt is
enabled, an SPI interrupt will occur. User software should always check the MSTR bit. If this bit is cleared by a
slave select and the user wants to continue to use the SPI as a master, the user must set the MSTR bit again,
otherwise it will stay in slave mode.
20.2.4 Transmit Holding Register Full Flag
To speed up the SPI transmit performance, a specially designed Transmit Holding Register (THR)
improves the latency time between byte to byte transmitting in CPU data moving. And a set THR-Full flag,
THRF (SPSTAT.5), indicates the data in THR is valid and waiting for transmitting. If THR is empty (THRF=0),
software writes one byte data to SPDAT will store the data in THR and set the THRF flag. If Output Shift
Register (OSR) is empty, hardware will move THR data into OSR immediately and clear the THRF flag. In SPI
mater mode, valid data in OSR triggers a SPI transmit. In SPI slave mode, valid data in OSR is waiting for
another SPI master to shift out the data. If THR is full (THRF=1), software writes one byte data to SPDAT will
set a write collision flag, WCOL (SPSTAT.6).
20.2.5 Write Collision