CMT2380F17
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20 Serial Peripheral Interface (SPI)
The CMT2380F17 provides a high-speed serial communication interface, the SPI interface. SPI is a
full-duplex,
high-speed and synchronous communication bus with two operation modes: Master mode and Slave
mode. Up to 24 Mbps can be supported in Master or 12MHz in Slave mode under a 48MHz system clock. It
has a Transfer Completion Flag (SPIF), Write Collision Flag (WCOL) and Mode Fault flag (MODF) in the SPI
status register (SPSTAT). And a specially designed Transmit Holding Register (THR) improves the transmit
performance compared to the conventional SPI and THRF flag indicates the THR is full or empty. SPIBSY
read-only flag reports the Busy state in SPI engine.
Figure 20-1. SPI Block Diagram
The SPI interface has four pins: MISO, MOSI, SPICLK and nSS:
SPICLK, MOSI and MISO are typically tied together between two or more SPI devices. Data flows
from master to slave on the MOSI pin (Master Out / Slave In) and flows from slave to master on the
MISO pin (Master In / Slave Out). The SPICLK signal is output in the master mode and is input in the
slave mode. If the SPI system is disabled, i.e., SPEN (SPCTL.6) = 0, these pins function as normal
I/O pins.
/SS is the optional slave select pin. In a typical configuration, an SPI master asserts one of its port
pins to select one SPI device as the current slave. An SPI slave device uses its nSS pin to
determine whether it is selected. The /SS is ignored if any of the following conditions are true:
If the SPI system is disabled, i.e. SPEN (SPCTL.6) = 0 (reset value).
If the SPI is configured as a master, i.e., MSTR (SPCTL.4) = 1, and nSS GPIO is configured as
an output.
If the /SS pin is ignored, i.e. SSIG (SPCTL.7) bit = 1, this pin is configured for port functions.
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