CMT2380F17
Rev0.1 | 290/347
www.cmostek.com
ADCFG0
：
ADC Configuration Register 0
SFR Page
= 0 Only
SFR Address = 0xC3
Bit
7
6
5
4
3
2
1
0
Name
ADCKS[2:0]
ADRJ
ACHS
SMPF
ADTM1
ADTM0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
0
0
0
0
X
X
0
0
Bit 7~5: ADC Conversion Clock Select bits.
ADCKS[2:0]
ADC Clock Selection
0 0 0
SYSCLK
0 0 1
SYSCLK/2
0 1 0
SYSCLK/4
0 1 1
SYSCLK/8
1 0 0
SYSCLK/16
1 0 1
SYSCLK/32
1 1 0
S0TOF/2
1 1 1
T2OF/2
Note:
1.
SYSCLK is the system clock.
2.
S0TOF is UART0 Baud-Rate Generator Overflow.
3.
T2OF is Timer2 Overflow.
Bit 4: ADRJ, ADC result Right-Justified selection.
0: The most significant 8 bits of conversion result are saved in ADCDH [7:0], while the least significant 2
bits in ADCDL[7:6].
1: The most significant 2 bits of conversion result are saved in ADCDH [1:0], while the least significant 8
bits in ADCDL[7:0].
(1) If ADRJ = 0
ADCDH
：
ADC Date High Byte Register
SFR Page
= 0~F
SFR Address = 0xC6
Bit
7
6
5
4
3
2
1
0
Name
ADCD[11:4]
R/W
R
R
R
R
R
R
R
R
Reset Value
X
X
X
X
X
X
X
X
Summary of Contents for CMT2380F17
Page 27: ...CMT2380F17 Rev0 1 27 347 www cmostek com 1 25 Phase Noise...
Page 177: ...CMT2380F17 Rev0 1 177 347 www cmostek com Figure 17 3 PCA Interrupt System...
Page 246: ...CMT2380F17 Rev0 1 246 347 www cmostek com SnMIPS S0MI S1MI 1 P3 3 P4 7...
