CMOSTEK CMT2380F17, Manual

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CMT2380F17
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28.3.2 Software approached ISP
The software approached ISP to make the MCU boot from the ISP-memory is to trigger a software reset
while the MCU is running in the AP-memory. In this case, neither HWBS nor HWBS2 is enabled. The only way
for the MCU to boot from the ISP-memory is to trigger a softwar
e reset, setting ISPCR.7~5 to “111”
simultaneously, when running in the AP-memory. Note: the ISP memory must be configured a valid space by
hardware option to reserve ISP mode for software approached ISP application.
Note: ISP storage space must configure a valid space through the hardware option to reserve the ISP mode to
start the ISP application by software.
28.3.3 Notes for ISP

Developing of the ISP Code
Although the ISP code is programmed in the ISP-
memory that has an ISP Start Address in the MCU’s
Flash (see Figure 28
–1 for MG82F6D17, it doesn’t mean you need to put this offset (= ISP Start Address) in
your source code. The code offset is automatically manipulated by the hardware. User just needs to develop it
like an application program in the AP-memory.

Interrupts during ISP
After triggering the ISP/IAP flash processing, the MCU will halt for a while for internal ISP processing until
the processing is completed. At this time, the interrupt will queue up for being serviced if the interrupt is
enabled previously. Once the processing is completed, the MCU continues running and the interrupts in the
queue will be serviced immediately if the interrupt flag is still active. The user, however, should be aware of
the following:
(1) Any interrupt can not be in-time serviced when the MCU halts for ISP processing.
(2) The low/high-level triggered external interrupts, nINTx, should keep activated until the ISP is
completed, or they will be neglected.

ISP and Idle mode
MG82F6D17 does not make use of idle-mode to perform ISP function. Instead, it freezes CPU running to
release the flash memory for ISP/IAP engine operating. Once ISP/IAP operation finished, CPU will be
resumed and advanced to the instruction which follows the previous instruction that invokes ISP/AP activity.

Accessing Destination of ISP
As mentioned previously, the ISP is used to program both the AP-memory and the IAP-memory. Once the
accessing destination address is beyond that of the last byte of the IAP-memory, the hardware will
automatically neglect the triggering of ISP processing. That is the triggering of ISP is invalid and the hardware
does nothing.

Flash Endurance for ISP
The endurance of the embedded Flash is 20,000 erase/write cycles, that is to say, the erase-then-write
cycles shouldn’t exceed 20,000 times. Thus the user should pay attention to it in the application which needs
to frequently update the AP-memory and IAP-memory.
。