CMT2380F17
Rev0.1 | 238/347
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0
0
0
Clear
TXD1
output register to
“0”
1
0
1
Clear
TXD1
output register to
“0”
2
1
0
Set
TXD1
output register to
“1”
3
1
1
Set
TXD1
output register to
“1”
For bit order control (DORD) on SPI serial transfer, MG82F6D17 provides a control bit, S1DOR, to
control the data bit order by software program. The default value of S1DOR is “1”, LSB first.
Transmission is initiated by any instruction that uses S1BUF as a destination register. The “write to
S1BUF” signal triggers the UART engine to start the transmission. The data in the S1BUF would be shifted
into the RXD1 pin as MOSI serial data. The SPI shift clock is built on the TXD1 pin for SPICLK output. After
eight raising edge of shift clocks passing, TI1 would be asserted by hardware to indicate the end of
transmission. And the contents on the S1MI pin would be sampled and shifted into shift register
. Then, “read
S1BUF” can get the SPI shift-in data. Figure 19–4 shows the transmission waveform in Mode 0. RI1 will not
be asserted in Mode 4.
Figure 19
–4. Serial Port 1 Mode 4 transmission waveform (n =1)
19.4
8-Bit Timer Mode on S1BRG
If the UART1 is not necessary in application or pending by software, setting S1TME=1 in the
MG82F6D17 provides the pure timer operating mode on S1 Baud Rate Generator (S1BRG). This timer
operates as an 8-bit auto-reload timer and provides the overflow flag which is set on the TI1 (S1CON.1). The
RI1 (S1CON.0) serves the port change detector on RXD1 port pin. Both of TI1 and RI1 in this mode keep the
interrupt capability on UART1 interrupt resource and have the individual interrupt enabled control (TB81 &
REN1). RB81 selects the RI1 detection level on RXD1 port input. If RB81=0, RI1 will be set by REN1=1 and
RXD1 pin falling edge detecting. Otherwise, RI1 will detect the rising edge on RXD1 port pin. In MCU
power-down mode, the RI1 is forced to level-sensitive operation and has the capability to wake up CPU if
UART1 interrupt is enabled.
This pure timer mode has a clock input option from Timer 1 overflow which is a cascaded counter to
perform a 16-bit timer. When S1BRC overflows, it can be the clock source of UART0 or toggle the port pin
output. “S1CKOE=1” enables the S1CKO output on port pin and masks the RI1 interrupt.
The configuration of the Pure Timer mode of S1BRG is shown in Figure 19
–5.
Summary of Contents for CMT2380F17
Page 27: ...CMT2380F17 Rev0 1 27 347 www cmostek com 1 25 Phase Noise...
Page 177: ...CMT2380F17 Rev0 1 177 347 www cmostek com Figure 17 3 PCA Interrupt System...
Page 246: ...CMT2380F17 Rev0 1 246 347 www cmostek com SnMIPS S0MI S1MI 1 P3 3 P4 7...
