CMOSTEK CMT2380F17, Manual, Page: 203 / 347

CMT2380F17
Rev0.1 | 203/347
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UART engine
TXBUF
RXBUF
RXD0
TXD0
SMOD1
RCLK
TCLK
TX Clock
Timer 1
Overflow
“
1
”
“
1
”
“
0
”
“
0
”
“
0
” “
1
”
Timer 2
Overflow
SYSCLK/2
“
0
” “
1
”
0
1
0
1
RX Clock
SM00
SM1
SM10
SM10
TB80
Mode 1, 3
clock source Mode 2
clock source
RCK
SMOD2
80C51 Internal BUS
Read
S0BUF
80C51 Internal BUS
Write
S0BUF
2 2
16
16 STOP-Bit
9th-Bit
0
1
SM00
RB80
TI0
RI0
Serial Port 0
Interrupt
BTI
System Flag
Interrupt
UTIE
ESF
Figure 18-6. Serial Port Mode 1, 2, 3
18.3 Serial Port 0 Mode 2 and Mode 3
11 bits are transmitted through TXD0, or received through RXD0: a start bit (0), 8 data bits (LSB first), a
programmable 9th data bit, and a stop bit (1). On transmit, the 9th data bit (TB80) can be assigned the value
of 0 or 1. On receive, the 9th data bit goes into RB80 in S0CON. The baud rate is programmable to select one
of 1/16, 1/32 or 1/64 the system clock frequency in Mode 2. Mode 3 may have a variable baud rate generated
from Timer 1 or Timer 2.
Figure 18
–2 shows the data frame in Mode 2 and Mode 3. Figure 18–5 shows a functional diagram of the
serial port in Mode 2 and Mode 3. The receive portion is exactly the same as in Mode 1. The transmit portion
differs from Mode 1 only in the 9th bit of the transmit shift register.
The “write to S0BUF” signal requests the Serial Port 0 Controller to load TB80 into the 9th bit position of
the transmit shit register and starts the transmission. After receiving a transmission request, the UART0
engine would start the transmission at the raising edge of TX Clock. The data in the S0BUF would be serial
output on the TXD0 pin with the data frame as shown in Figure 18
–2 and data width depend on TX Clock.
After the end of 9th data transmission, TI0 would be asserted by hardware to indicate the end of data
transmission and its interrupt vector can be switched to System Flag interrupt by BTI and UTIE gated.
Reception is initiated when the UART0 engine detected 1-to-0 transition at RXD0 sampled by RCK. The
data on the RXD0 pin would be sampled by Bit Detector in UART0 engine. After the end of 9th data bit
reception, RI0 would be asserted by hardware to indicate the end of data reception and load the 9th data bit
into RB80 in S0CON register.
In all four modes, transmission is initiated by any instruction that use S0BUF as a destination register.
Reception is initiated in mode 0 by the condition RI0 = 0 and REN0 = 1. Reception is initiated in the other
modes by the incoming start bit with 1-to-0 transition if REN0=1.