CMOSTEK CMT2380F17, Manual

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CMT2380F17
Rev0.1 | 225/347
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Bit 6: SMOD0, Frame Error select. 0: S0CON.7 is SM0 function.
1: S0CON.7 is FE function. Note that FE will be set after a frame error regardless of the state of SMOD0.

S0CFG
：
Serial Port 0 Configuration Register
SFR Page = 0 only
SFR Address = 0x9C RESET = 0000-1000
Bit
7 6 5 4 3 2 1 0
Name
URTS SMOD2 URM0X3 SM30 S0DOR BTI UTIE SMOD3
R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Reset Value
0 0 0 0 1 0 0 0
Bit 7: URTS, UART0 Timer Selection.
0: Timer 1 or Timer 2 can be used as the Baud Rate Generator in Mode 1 and Mode 3.
1: Timer 1 overflow signal is replaced by the UART1 Baud Rate Timer overflow signal when Timer 1 is
selected as the Baud Rate Generator in Mode1 or Mode 3 of the UART0. (Refer Section “18.7.4 Baud
Rate in Mode 1 & 3”.)
Bit 6: SMOD2, UART0 extra double baud rate selector. 0: Disable extra double baud rate for UART0.
1: Enable extra double baud rate for UART0.
Bit 5: URM0X3, this bit control the baud rate in S0 mode 0, mode 2 and mode 4. S1 in mode 0 and
mode4:
0: Clear to select SYSCLK/12 as the baud rate for S0 Mode 0 and Mode 4. 1: Set to select SYSCLK/4 as
the baud rate for S0 Mode 0 and Mode 4.
S0 in mode 2:
0: Clear to select UART0 baud rate as SYSCLK/32 or /64. 1: Set to select UART0 baud rate as
SYSCLK/96 or /192.
Bit 4: SM30, Serial Port Mode control bit 3.
Bit 3: S0DOR, Serial Port 0 data order control in all operating modes. If S0 is not in Timer mode:
0: The MSB of the data byte is transmitted first.
1: The LSB of the data byte is transmitted first. S0DOR is set to “1” in default. If S0 is in Timer mode:
0: Set the S0BRG to 8-bit reload timer/counter mode. 1: Set the S0BRG to 16-bit timer/counter mode.
Bit 2: BTI, Block TI0 in Serial Port 0 Interrupt.
0: Retain the TI0 to be a source of Serial Port 0 Interrupt.
1: Block TI0 to be a source of Serial Port 0 Interrupt.
Bit 1: UTIE, S0 TI0 Enabled in system flag interrupt.
0: Disable the interrupt vector sharing for TI0 in system flag interrupt.
1: Set TI0 flag will share the interrupt vector with system flag interrupt.
Bit 0: SMOD3, S0CR1 access control.
0: Disable S0CR1 access. CPU accesses SFR address 0xB9 to read/write SADEN.
1: Enable S0CR1 access. CPU accesses SFR address 0xB9 to read/write S0CR1.

AUXR2
：
Auxiliary Register 2
SFR Page = 0~F
SFR Address = 0xA3
Bit 7 6 5 4 3 2 1 0
Name STAF STOF -- -- T1X12 T0X12 T1CKOE T0CKOE
R/W R/W R/W W W R/W R/W R/W R/W
Reset Value 0 0 0 0 0 0 0 0