CMOSTEK CMT2380F17, Manual, Page: 59 / 347

CMT2380F17
Rev0.1 | 59/347
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For example 1:
The source data is selected on ADC12 and the destination data is selected on XRAM. Then, DMA
controller will move data from the ADC12 conversion result register ADCDH and ADCDL to 8051 XRAM. The
DMA transfer type is peripheral to XRAM. And software must avoid the read operation on ADCDH and
ADCDL.
For example 2:
The source data is selected on ADC12 and the destination data is selected on S0 TX. Then, DMA
controller will move data from the ADC12 conversion result register ADCDH and ADCDL to S0BUF. The DMA
transfer type is peripheral to peripheral. Software must avoid to read ADCDH, ADCDL and to write data to
S0BUF.
The configuration of DMA data path selection is listed in below Table 8
–1.
Table8-1. DMA Data Path Selection
DSS30~00
(DMADS0[7:4])
Source Selection
DDS30~00
(DMADS0[3:0])
Destination Selection
0 0 0 0 Disabled 0 0 0 0 Disabled
0 0 0 1 S0RX 0 0 0 1 S0TX
0 0 1 0 S1RX 0 0 1 0 S1TX
0 1 0 1 TWI0RX 0 1 0 1 TWI0TX
0 1 1 1 SPI0RX 0 1 1 1 SPI0TX
1 0 0 1 ADC0 1 0 0 1
保留
1 1 0 1
保留
1 1 0 1 CRC
1 1 1 1 XRAM 1 1 1 1 XRAM
8.2.2 DMA Transfer Mode
The DMA controller in CMT2380F17 only supports block transfer mode. After DMA trigger active, DMA
controller start to move data until the overflow event happened on DMA Current Transfer Count. That is one
trigger input to activate a block data transfer by DMA controller.
The block data transfer size is defined in {TH5+TL5} as DMA Current Transfer Count. It supports the
transfer size from 1 DMA transaction to 65536 DMA transactions. In CMT2380F17, one DMA transaction
move one byte data from source to destination.
。
8.2.3 Transfer Count & Address Pointer
DMA transfer count control and memory address pointer are implemented on Timer 5 and Timer 6 in
DMA module. The action of Timer 5 and Timer 6 likes general Timer 0 with 16-bit counter (TH5 + TL5, TH6 +
TL6) and 16-bit reload register (THR5 + TLR5, THR6 + TLR6). If DMA enabled, Timer 5 controls the DMA
transfer count and Timer 6 points to memory address. Both of Timer 5 and Timer 6 is always 16-bit up-count
counter.
The Current Transfer Count implemented on {TH5 + TL5} register determines the number of transactions
to be performed. The Base Transfer Count is implemented on {THR5 + TLR5}. It supports the maximum
transfer count is up to 65536. The actual transfer count is equal to the value of (65536
– {TH5 + TL5}). The
Current Transfer Count is increment after each DMA transaction. When the value in the register goes from
FFFFH to 0000H, an event at
“End of DMA transfer” is generated to stop the DMA transfer by clear DMAS0
and set DMA Complete Flag (DCF0). The event also reloads {THR5 + TLR5} to {TH5 + TL5} to initialize the
new Current Transfer Count for next DMA transfer.