CMOSTEK CMT2380F17, Manual

Page: 222 / 347

CMT2380F17
Rev0.1 | 222/347
www.cmostek.com
Mode 4
(Master)
Slave #1
SnMI
RXDn
TXDn
Port Pin 1
MISO
MOSI
SPICLK
nSS
Slave #2
MISO
Port Pin 2 nSS
SPICLK
MOSI
MCU Serial Port n
Figure 18-12. Serial Port 0 Mode 4, Single Master and Multiple Slaves configuration (n = 0)
The SPI master satisfies the transfer with the full function SPI module of Megawin MG82/84 series MCU
with CPOL, CPHA and DORD selection. For CPOL and CPHA condition, MG82F6D17 uses an easy way by
initialize SPI clock assigned port pin (TXD0, P3.1/P4.5) polarity to fit them. Table 18
–39 shows the serial port
Mode 4 mapping with the four SPI operating mode.
Table 18-39. SPI mode mapping with Serial Port Mode 4 configuration
SPI Mode CPOL CPHA Configuration in TXD0
0 0 0 Clear TXD0 output register to
“0”
1 0 1 Clear TXD0 output register to
“0”
2 1 0 Set TXD0 output register to
“1”
3 1 1 Set TXD0 output register to
“1”
For bit order control (DORD) on SPI serial transfer, MG82F6D17 provides a control bit, S0DOR, to control
the data bit order by
software program. S0DOR default is “1”, LSB first.
Transmission is initiated by any instruction that uses S0BUF as a destination register. The “write to
S0BUF” signal triggers the UART engine to start the transmission. The data in the S0BUF would be shifted
into the RXD0 pin as MOSI serial data. The SPI shift clock is built on the TXD0 pin for SPICLK output. After
eight raising edge of shift clocks passing, TI0 would be asserted by hardware to indicate the end of
transmission. And the contents on the S0MI
pin would be sampled and shifted into shift register. Then, “read
S0BUF” can get the SPI shift-in data. Figure 18–13 shows the transmission waveform in Mode 0. RI0 will not
be asserted in Mode 4.
Write to SnBUF
TXDn
(SPICLK)
RXDn
(MOSI)
TIn
RIn
D0 D1 D2 D3 D4 D5 D6 D7
Software set/clear TXDn assigned port pin to initial clock polarity
D0 D1 D2 D3 D4 D5 D6 D7
SnMI
(MISO)