CMT2380F17
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transfer by one DMA trigger, on CPU software trigger or external hardware trigger. The transfer size is
programmable from 1 to 65536 and this function is implemented on Timer 5 for DMA transfer count. If DMA
needs to access XRAM, the Timer 6 implements the XRAM address pointer. When DMA finishes one data
transaction, DMA_CLK will trigger Timer 5 to increase the DMA transfer count and increase Timer 6 to point
next XRAM address. Both of Timer 5 and Timer 6 only support up-count operation. When DMA function is not
in used, the Timer 5 and Timer 6 can be traded as a general Timer 0 with 16-bit counter.
DMACR0 and DMACG0 are the SFRs for DMA operation mode control. It includes DMA start, suspend,
interrupt enabled….etc. In DMA Operation section, will introduce the function in detailed.
The DMA controller block diagram is shown in Figure 8
–2.
。
DMA Control Logic
DCF0
DIE0
SFR Address
Decoder
DMA CH0
Complete Interrupt
DMA Complete Flag
overflow
16-bit Up Counter
Current Address
{TH6 + TL6}
Base Address
{THR6 + TLR6}
reload
16-bit Up Counter
(1~65536 bytes)
Current Transfer Count
{TH5 + TL5}
Base Transfer Count
{THR5 + TLR5}
DMA CLK
DMA XRAM Address
(A15~A0)
CPU Halt
DMA XRAM RD/WR
DMA SFR RD/WR
XRAM Data 7~0
SFR_Data 7~0
CPU software trigger
External hardware trigger
DMA SFR Address
(A7~A0)
DSS10 DSS20 DSS10 DSS00
DDS30 DDS20 DDS10 DDS00
DMADS0
Figure 8-2. DMA Structure
8.2
DMA Operation
The DMA controller is configured with user software. The setup and operation of the DMA is discussed in
the following sections.
8.2.1
DMA Transfer Types
The DMA controller in CMT2380F17 supports 3 type data transfer as following list:
：
M2P: XRAM to Peripheral
P2M: Peripheral to XRAM P2P:
Peripheral to Peripheral
The DMA controller does not support the data transfer for XRAM to XRAM (M2M). It also cannot access
the internal data RAM area and flash ROM area. The DMA transfer type is defined by DMADS0 when
software configures the DMA data path of source and destination. Otherwise, if a peripheral is configured for
DMA access, software must not access the data register of the peripheral.
Summary of Contents for CMT2380F17
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