CMT2380F17
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Figure 16-22. Split Timer 2 in Baud-Rate Generator Mode
16.2.11
Timer 2 Programmable Clock Output
Timer 2 has a Clock-Out Mode (while CP/RL2=0 & T2OE=1). In this mode, Timer 2 operates as a
programmable clock generator with 50% duty-cycle. The generated clocks come out on P1.0. The input clock
(SYSCLK/2 or SYSCLK) increments the 16-bit timer (TH2, TL2). The timer repeatedly counts to overflow from
a loaded value. Once overflows occur, the contents of (RCAP2H, RCAP2L) are loaded into (TH2, TL2) for the
consecutive counting. Figure 16
–23 gives the formula of Timer 2 clock-out frequency: Figure 16–24 shows the
clock structure of Timer 2.
T2 Clock Frequency
2 x (65536
–
(RCAP2H, RCAP2L))
T2 Clock-out Frequency =
Figure 16-23. Timer 2 clock out equation
Note:
(1) Timer 2 overflow flag, TF2, will be set when Timer 2 overflows to generate interrupt. But, the TF2
interrupt can be blocked by TF2IG in T2MOD1 register.
(2) For SYSCLK=12MHz and select SYSCLK/12 as Timer 2 clock source, Timer 2 has a programmable
output frequency range from 45.7Hz to 3MHz.
(3) For SYSCLK=12MHz and select SYSCLK as Timer 2 clock source, Timer 2 has a programmable output
Summary of Contents for CMT2380F17
Page 27: ...CMT2380F17 Rev0 1 27 347 www cmostek com 1 25 Phase Noise...
Page 177: ...CMT2380F17 Rev0 1 177 347 www cmostek com Figure 17 3 PCA Interrupt System...
Page 246: ...CMT2380F17 Rev0 1 246 347 www cmostek com SnMIPS S0MI S1MI 1 P3 3 P4 7...