CMOSTEK CMT2380F17, Manual

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CMT2380F17
Rev0.1 | 154/347
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TL2IS (T2MOD1.5) must be cleared to enable access to the TCLK bit.
Bit 4: TCLK, Transmit clock flag.
0: Causes Timer 1 overflows to be used for the transmit clock.
1: Causes the serial port to use Timer 2 overflow pulses for its transmit clock in modes 1 and 3.
TL2IS (T2MOD1.5) must be set to enable access to the TL2IE bit.
Bit 4: TL2IE, TF2L interrupt enable.
0: Disable TF2L interrupt.
1: Enable TF2L interrupt to share the Timer 2 interrupt vector.
Bit 3: EXEN2, Timer 2 external enable flag on a negative transition of T2EX pin.
0: Cause Timer 2 to ignore negative transition events at T2EX pin.
1: Allows a capture or reload to occur as a result of a 1-to-0 transition on T2EX pin if Timer 2 is not being
used to clock the serial port 0. If Timer 2 is configured to clock the serial port 0, the T2EX remains the
external transition detection and reports on EXF2 flag with Timer 2 interrupt.
Bit 2: TR2, Timer 2 Run control bit. If in Timer 2 split mode, it only controls the TH2.
0: Disabled to stop the Timer/Counter 2.
1: Enabled to start the Timer/Counter 2.
Bit 1: C/T2, Timer 2 clock or counter source selector. The function is active with T2X12 and T2CKS as
following definition:
T2CKS, T2X12, C/T2 Timer 2 Clock Selection
TH2 Clock Selection in
split mode
0 0 0 SYSCLK/12 SYSCLK/12
0 0 1 T2 Pin T2 Pin
0 1 0 SYSCLK SYSCLK
0 1 1 INT0ET TL2OF
1 0 0 S0TOF S0TOF
1 0 1 T0OF T0OF
1 1 0 Reserved Reserved
1 1 1 KBIET KBIET
Bit 0: CP/RL2, Timer 2 mode control bit. Refer T2MOD.T2MS0 description for the function definition.

T2MOD
：
Timer 2 Mode Register
SFR Page = 0 Only
SFR Address = 0xC9
Bit
7 6 5 4 3 2 1 0
Name
T2SPL TL2X12 T2EXH T2X12 TR2L TR2LC T2OE T2MS0
R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Reset Value
0 0 0 0 0 0 0 0
Bit 7: T2SPL, Timer 2 split mode control.
0: Disable Timer 2 to split mode.
1: Enable Timer 2 to split mode.
Bit 6: TL2X12, the clock control bit of TL2 in Timer 2 split mode.
TL2CS, TL2X12 TL2 Clock Selection
0 0 SYSCLK/12
0 1 SYSCLK
1 0 S0TOF
1 1 INT0ET
Bit 5: T2EXH, Timer 2 external enable flag on a positive transition of T2EX pin. 0: Cause Timer 2 to