CMOSTEK CMT2380F17, Manual, Page: 89 / 347

CMT2380F17
Rev0.1 | 89/347
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13.2.8 Interrupt Recovery from Power-down
3 external interrupts may be configured to terminate Power-down mode. External interrupts nINT0, nINT1,
nINT2 may be used to exit Power-down. To wake up by external interrupt nINT0, nINT1, nINT2, the interrupt
must be enabled and configured for level-sensitive operation. If the enabled external interrupts are configured
to edge-sensitive operation (Falling or Rising), they will be forced to level-sensitive operation (Low level or
High level) by hardware in power-down mode.
When terminating Power-down by an interrupt, the wake up period is internally timed. At the falling edge
on the interrupt pin, Power-down is exited, the oscillator is restarted, and an internal timer begins counting.
The internal clock will not be allowed to propagate and the CPU will not resume execution until after the timer
has reached internal counter full. After the timeout period, the interrupt service routine will begin. To prevent
the interrupt from re-triggering, the ISR should disable the interrupt before returning. The interrupt pin should
be held low until the device has timed out and begun executing.
13.2.9 Reset Recovery from Power-down
Wakeup from Power-down through an external reset is similar to the interrupt. At the rising edge of RST,
Power-down is exited, the oscillator is restarted, and an internal timer begins counting. The internal clock will
not be allowed to propagate to the CPU until after the timer has reached internal counter full. The RST pin
must be held high for longer than the timeout period to ensure that the device is reset properly. The device will
begin executing once RST is brought low.
It should be noted that when idle is terminated by a hardware reset, the device normally resumes
program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes
control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not
inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the
instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.
13.2.10 KBI wakeup Recovery from Power-down
The Keypad Interrupt of CMT2380F17, KBI.7~0 have wakeup CPU capability that are enabled by the
control registers in KBI module. OR software can configure the KBI inputs on different port pins. Please refer
Section “30 Auxiliary SFRs” for more detailed AUXR6 information.
Wakeup from Power-down through an enabled wakeup KBI is same to the interrupt. At the matched
condition of enabled KBI pattern and enabled KBI interrupt (EIE1.5, EKB), Power-down is exited, the oscillator
is restarted, and an internal timer begins counting. The internal clock will not be allowed to propagate to the
CPU until after the timer has reached internal counter full. After the timeout period, CPU will meet a KBI
interrupt and execute the interrupt service routine.
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13.3 Power Control Register

PCON0 : Power Control Register 0
SFR Page = 0~F & P
SFR Address = 0x87 POR = 0001-0000, RESET = 000X-0000
Bit 7 6 5 4 3 2 1 0
Name SMOD[1:0] GF POF0 GF[1:0] PD IDL
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset Value 0 0 0 1 0 0 0 0